CS/ECE 552 Introduction to Computer Architecture Spring 2012 Section 1 Instructor David A. Wood and T. A. Ramkumar Ravikumar URL: http://www.cs.wisc.edu/~david/courses/cs552/S12/

CS552 Class Project

Documents

• General Summary

• Deadlines and Grading

• Suggested Project Stages

• Verilog file naming conventions

• Microarchitecure Specification

• Instruction Set Architecture

• Sharing Files and SVN

• Test Code

• Project Teams

• Interpreation of immediate and displacement fields (updated 3/14)

• Demo I submission instructions (updated 03/22/12)

• Demo II submission instructions (updated 04/20/12)

• Verification for Demo II (added 04/20/12)

• Demo III instructions (updated 04/28/12)

• Info on Zero delay oscillation loops (added 04/19/12)

Tools

• WISC-SP12 Assembler

• WISCALCULATOR - The WISC-SP12 simulator/debugger (working in both mumble and king lab machines)

• wsrun.pl - Command Line Verilog Simulation

• synth.pl – AutoMagic Synthesis Tool

• Vcheck

• Cache Simulator

(Add /p/course/cs552-david/public/html/S12/handouts/bins to your path to use these tools. )

Project Modules:

Basic Modules:
D-FlipFlop
Clock-Reset Module – (Updated 3/2/2012)

Top Level Processor Modules:
proc.v  -  Your Processor
proc_hier.v -  Your Processor with clk-rst module added.
proc_hier_bench.v – Testbench for Non-pipelined Processor
proc_hier_pbench.v -  Testbench for Pipelined Processor  (use wsrun.pl -pipe)

Memories:
Single Cycle Memory
Single Cycle Aligned Memory
Stalling Memory
Four Banked Memory

Cache Module