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cpu_policy.hh
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1 /*
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29  * Authors: Kevin Lim
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31 
32 #ifndef __CPU_O3_CPU_POLICY_HH__
33 #define __CPU_O3_CPU_POLICY_HH__
34 
35 #include "cpu/o3/comm.hh"
36 #include "cpu/o3/commit.hh"
37 #include "cpu/o3/decode.hh"
38 #include "cpu/o3/fetch.hh"
39 #include "cpu/o3/free_list.hh"
40 #include "cpu/o3/iew.hh"
41 #include "cpu/o3/inst_queue.hh"
42 #include "cpu/o3/lsq.hh"
43 #include "cpu/o3/lsq_unit.hh"
44 #include "cpu/o3/mem_dep_unit.hh"
45 #include "cpu/o3/regfile.hh"
46 #include "cpu/o3/rename.hh"
47 #include "cpu/o3/rename_map.hh"
48 #include "cpu/o3/rob.hh"
49 #include "cpu/o3/store_set.hh"
50 
60 template<class Impl>
62 {
68  typedef ::ROB<Impl> ROB;
72  typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
74  typedef ::LSQ<Impl> LSQ;
76  typedef ::LSQUnit<Impl> LSQUnit;
77 
88 
91 
94 
97 
100 
102  typedef ::IssueStruct<Impl> IssueStruct;
103 
106 
107 };
108 
109 #endif //__CPU_O3_CPU_POLICY_HH__
DefaultFetch< Impl > Fetch
Typedef for fetch.
Definition: cpu_policy.hh:79
Struct that defines the information passed from IEW to commit.
Definition: comm.hh:94
DefaultRename handles both single threaded and SMT rename.
Definition: rename.hh:70
::LSQ< Impl > LSQ
Typedef for the LSQ.
Definition: cpu_policy.hh:74
DefaultCommit< Impl > Commit
Typedef for commit.
Definition: cpu_policy.hh:87
DefaultRenameDefaultIEW< Impl > RenameStruct
The struct for communication between rename and IEW.
Definition: cpu_policy.hh:96
DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:80
DefaultDecode class handles both single threaded and SMT decode.
Definition: decode.hh:61
DefaultRename< Impl > Rename
Typedef for rename.
Definition: cpu_policy.hh:83
::LSQUnit< Impl > LSQUnit
Typedef for the thread-specific LSQ units.
Definition: cpu_policy.hh:76
DefaultCommit handles single threaded and SMT commit.
Definition: commit.hh:83
DefaultDecode< Impl > Decode
Typedef for decode.
Definition: cpu_policy.hh:81
DefaultFetch class handles both single threaded and SMT fetch.
Definition: fetch.hh:71
Unified register rename map for all classes of registers.
Definition: rename_map.hh:159
DefaultDecodeDefaultRename< Impl > DecodeStruct
The struct for communication between decode and rename.
Definition: cpu_policy.hh:93
Struct that defines the information passed from fetch to decode.
Definition: comm.hh:61
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:95
Struct that defines the key classes to be used by the CPU.
Definition: cpu_policy.hh:61
::ROB< Impl > ROB
Typedef for the ROB.
Definition: cpu_policy.hh:68
Struct that defines the information passed from rename to IEW.
Definition: comm.hh:84
Struct that defines all backwards communication.
Definition: comm.hh:122
InstructionQueue< Impl > IQ
Typedef for the instruction queue/scheduler.
Definition: cpu_policy.hh:70
::IssueStruct< Impl > IssueStruct
The struct for communication within the IEW stage.
Definition: cpu_policy.hh:102
DefaultIEW< Impl > IEW
Typedef for Issue/Execute/Writeback.
Definition: cpu_policy.hh:85
DefaultFetchDefaultDecode< Impl > FetchStruct
The struct for communication between fetch and decode.
Definition: cpu_policy.hh:90
UnifiedFreeList FreeList
Typedef for the freelist of registers.
Definition: cpu_policy.hh:64
A standard instruction queue class.
Definition: inst_queue.hh:82
DefaultIEWDefaultCommit< Impl > IEWStruct
The struct for communication between IEW and commit.
Definition: cpu_policy.hh:99
TimeBufStruct< Impl > TimeStruct
The struct for all backwards communication.
Definition: cpu_policy.hh:105
Struct that defines the information passed from decode to rename.
Definition: comm.hh:74
UnifiedRenameMap RenameMap
Typedef for the rename map.
Definition: cpu_policy.hh:66
::MemDepUnit< StoreSet, Impl > MemDepUnit
Typedef for the memory dependence unit.
Definition: cpu_policy.hh:72

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