35 #ifndef __TSUNAMI_CCHIP_HH__
36 #define __TSUNAMI_CCHIP_HH__
40 #include "params/TsunamiCChip.hh"
132 void reqIPI(uint64_t ipreq);
138 #endif // __TSUNAMI_CCHIP_HH__
Tsunami * tsunami
pointer to the tsunami object.
void postDRIR(uint32_t interrupt)
post an interrupt to the CPU.
void postRTC()
post an RTC interrupt to the CPU
void reqIPI(uint64_t ipreq)
request an interrupt be posted to the CPU.
uint64_t drir
This register contains bits for each PCI interrupt that can occur.
TsunamiCChip(const Params *p)
Initialize the Tsunami CChip by setting all of the device register to 0.
Top level class for Tsunami Chipset emulation.
uint64_t ipint
Indicator of which CPUs have an IPI interrupt.
static const int Max_CPUs
Max number of CPUs in a Tsunami.
uint64_t dim[Tsunami::Max_CPUs]
The dims are device interrupt mask registers.
TsunamiCChipParams Params
void clearIPI(uint64_t ipintr)
post an ipi interrupt to the CPU.
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
uint64_t Tick
Tick count type.
void serialize(CheckpointOut &cp) const override
Serialize an object.
Declaration of top level class for the Tsunami chipset.
const Params * params() const
void clearITI(uint64_t itintr)
clear a timer interrupt previously posted to the CPU.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Tsunami CChip CSR Emulation.
std::ostream CheckpointOut
const SimObjectParams * _params
Cached copy of the object parameters.
uint64_t dir[Tsunami::Max_CPUs]
The dirs are device interrupt registers.
void clearDRIR(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
uint64_t itint
Indicator of which CPUs have an RTC interrupt.