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Click here for one-page pdf overview.
All events will be held at the Monona Terrace Convention Center.
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Saturday breakfast, breaks, and lunches are in Grand Terrace West.
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See
Tutorials and Workshops page.
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| 8:00-9:00 | Breakfast (Grand Terrace West) |
9:00-5:30
All Day Events |
Tutorial T1: Design and Implementation of the TRIPS EDGE Architecture
(Room E)
Doug Burger, UT Austin
Stephen W. Keckler, UT Austin
Robert McDonald, UT Austin
Ramdas Nagarajan, UT Austin
Nitya Ranganathan, UT Austin
Haiming Liu, UT Austin
Karu Sankaralingam, UT Austin
Simha Sethumadhavan, UT Austin
Changkyu Kim, UT Austin
Paul Gratz, UT Austin
PK Shivakumar, UT Austin
Heather Hanson, UT Austin
Kathryn McKinley , UT Austin
William Yoder, UT Austin
Aaron Smith, UT Austin
Xia Chen, UT Austin
Tutorial T2: Robust System Design from Unreliable Components (Room F)
Subhasish Mitra, Intel Corporation & Stanford University
Vijay Narayanan, Penn State
Lisa Spainhower, IBM
Yuan Xie, Penn State
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9:00-12:30
Morning Event |
Workshop W1: Advanced Networking and Communications Hardware Workshop (ANCHOR) (Room H)
Taskin Kocak, University of Central Florida
Gokhan Memik, Northwestern University
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11:00-6:40
Three-Quarter
Day Event |
Workshop W2: Workshop on Modeling, Benchmarking and Simulation (MOBS) (Room I)
Lieven Eeckhout, Ghent University
Joshua Yi, Freescale Semiconductor
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| 12:30-2:00 |
Lunch (Grand Terrace West) |
2:00-6:15
Afternoon Event |
Workshop W3: Fourth Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD) (Room H)
Bryan Black, Intel Corp
Harold Cain, IBM Research
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| 9:00-??? |
Official Unofficial Nighttime Event
(Memorial Union Terrace) |
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Sunday breakfast, breaks, and lunches are in Grand Terrace West.
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See
Tutorials and Workshops page.
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| 8:00-9:00 | Breakfast (Grand Terrace West) |
8:30-5:30
All Day Event |
Workshop W4: Workshop on Computer Architecture Education (WCAE) (Room I)
Edward F. Gehringer, North Carolina State University
Kenneth G. Ricks, The University of Alabama
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9:00-12:30
Morning Events |
Tutorial T3: GEMS: Multifacet's General Execution-driven Multiprocessor
Simulator (Room E&F) (slides)
Mike Marty, UW Madison
Bradford Beckmann, UW Madison
Luke Yen, UW Madison
Alaa R. Alameldeen, UW Madison
Min Xu, UW Madison
Kevin E. Moore, UW Madison
Workshop W5: Workshop on Complexity-Effective Design (WCED) (Room H)
David H. Albonesi, Cornell University
Pradip Bose, IBM T.J. Watson Research Center
Prabhakar Kudva, IBM T.J. Watson Research Center
Diana Marculescu, Carnegie Mellon University
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| 12:30-2:00 | Lunch (Grand Terrace West) |
2:00-5:30
Afternoon Events |
Tutorial T4: Using the M5 Simulator (Room E&F)
Steven K. Reinhardt, U Michigan
Nathan L. Binkert, U Michigan
Ronald G. Dreslinski, U Michigan
Lisa R. Hsu, U Michigan
Kevin T. Lim, U Michigan
Ali G. Saidi, U Michigan
Workshop W6: Second Workshop on Temperature-Aware Computer
Systems (TACS) (Room H)
(ends at 6:00 not 5:30)
Kevin Skadron, University of Virginia
David Brooks, Harvard Division of Engineering and Applied
Sciences
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| 3:00-5:00 |
The First (Annual?) ISCA Hockey Game (3:00-5:00)
- Organizers:
- Adam Butts, IBM Research
- David Wood, UW Madison
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| 6:00-7:30 |
Welcome Reception (Rooftop, West Circle)
Generous corporate support provided by Google
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| 9:00-??? |
Official Unofficial Nighttime Event
(Great Dane Pub) |
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All the A sessions are in Ballroom A; all the B
sessions are in Ballrom B. All the joint sessions are in Ballroom A&B (merged).
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Many ISCA05 authors graciously provided their presentations slides
in PPT or PDF, which we have linked as "(slides)" after the
corresponding talk titles. We do NOT have slides for titles NOT
followed by "(slides)".
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| 8:00-9:00 | Breakfast (Capitol Promenade) |
| 9:00-9:15 |
Welcome, Gurindar Sohi, Mark Hill, and David Wood |
| 9:15-9:25 |
Remarks (slides),
David Patterson, President of the ACM |
| 9:25-10:25 |
Keynote Address: Dataflow: Passing the Token
(slides)
Arvind, Johnson Professor, MIT
Chair: Mark Hill, University of Wisconsin, Madison
(unauthorized reading assignment)
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| 10:30-11:00 | Break (Capitol Promenade) |
| 11:00-12:30 |
SESSION 1: SECURITY
Chair: David Patterson, University of California, Berkeley
Architecture for Protecting Critical Secrets in Microprocessors
(slides)
Ruby B. Lee, Princeton University
Peter C. S. Kwan, Princeton University
Patrick McGregor, Princeton University
Jeffrey Dwoskin, Princeton University
Zhenghong Wang, Princeton University
High Efficiency Counter Mode Security Architecture via Prediction and
Precomputation
Weidong Shi, Georgia Tech
Hsien-Hsin S.Lee, Georgia Tech
Mrinmoy Ghosh, Georgia Tech
Chenghuai Lu, Georgia Tech
Alexandra Boldyreva, Georgia Tech
Design and Implementation of the AEGIS Single-Chip Secure Processor Using
Physical Random Functions
(slides)
G. Edward Suh, MIT
Charles W. O'Donnell, MIT
Ishan Sachdev, MIT
Srinivas Devadas, MIT
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| 12:30-2:00 | Lunch (Grand Terrace)
Generous corporate support provided by Intel
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| 2:00-3:30 |
SESSION 2A: INTERACTING WITH DISKS & NETWORKS
Chair: Luiz Barroso, Google
Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal
Management
(slides)
Sudhanva Gurumurthi, Pennsylvania State University
Anand Sivasubramaniam, Pennsylvania State University
Vivek K. Natarajan, Pennsylvania State University
Direct Cache Access for High Bandwidth Network I/O
Ram Huggahalli, Communication Technology Lab, Intel Corporation
Ravi Iyer, Communication Technology Lab, Intel Corporation
Scott Tetrick, Digital Enterprise Group, Intel Corporation
Deconstructing Commodity Storage Clusters
(slides)
Haryadi S. Gunawi, University of Wisconsin - Madison
Nitin Agrawal, University of Wisconsin - Madison
Andrea C. Arpaci-Dusseau, University of Wisconsin - Madison
Remzi H. Arpaci-Dusseau, University of Wisconsin - Madison
Jiri Schindler, EMC Corp.
SESSION 2B: MEMORY COMPRESSION & RENAMER OPTIMIZATIONS
Chair: André Seznec, IRISA/INRIA
A Robust Main-Memory Compression Scheme
(slides)
Magnus Ekman, Chalmers University of Technology
Per Stenström, Chalmers University of Technology
Continuous Optimization
(slides)
Brian Fahs, University of Illinois, Urbana-Champaign
Todd Rafacz, University of Illinois, Urbana-Champaign
Sanjay J. Patel, University of Illinois, Urbana-Champaign
Steven S. Lumetta , University of Illinois, Urbana-Champaign
RENO - A Rename-based Instruction Optimizer
(slides)
Vlad Petric, University of Pennsylvania
Tingting Sha, University of Pennsylvania
Amir Roth, University of Pennsylvania
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| 3:30-4:00 | Break (Capitol Promenade) |
| 4:00-5:30 |
SESSION 3A: SPECIALIZED PROCESSORS
Chair: Kathryn McKinley, University of Texas, Austin
A High Throughput String Matching Architecture for Intrusion Detection and
Prevention
(slides)
Lin Tan, UC Santa Barbara
Timothy Sherwood, UC Santa Barbara
A Tree Based Router Search Engine Architecture With Single Port Memories
Florin Baboescu, University of California, San Diego
Dean Tullsen, University of California, San Diego
Grigore Rosu, University of Illinois, Urbana-Champaign
Sumeet Singh, University of California, San Diego
An Integrated Memory Array Processor Architecture for Embedded Image
Recognition Systems
(slides)
Shorin Kyo, NEC Corporation
Shin'ichiro Okazaki, NEC Corporation
Tamio Arai, University of Tokyo
SESSION 3B: DETECTING FAULTS
Chair: Kevin Skadron, University of Virginia
Design and Evaluation of Hybrid Fault-Detection Systems
(slides)
George A. Reis, Princeton University
Jonathan Chang, Princeton University
Neil Vachharajani, Princeton University
Ram Rangan, Princeton University
David I. August, Princeton University
Shubu Mukherjee, Intel
Rescue: A Microarchitecture for Testability and Defect Tolerance
(slides)
Ethan Schuchman, Purdue University
T.N. Vijaykumar, Purdue University
Opportunistic Transient-Fault Detection
(slides)
Mohamed A. Gomaa, Purdue University
T. N. Vijaykumar, Purdue University
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| 6:00-9:00 |
Concert and Reception
(Overture Center)
Generous corporate support provided by Sun Microsystems
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| 9:00-??? |
Official Unofficial Nighttime Event
(Memorial Union Terrace) |
| 8:00-9:00 | Breakfast (Capitol Promenade) |
| 9:00-10:30 |
SESSION 4A: QUANTUM COMPUTING & VERY LOW POWER
Chair: Norman Jouppi, HP
An Evaluation Framework and Instruction Set Architecture for Ion-Trap based
Quantum Micro-architectures
Steven Balensiefer, University of Washington
Lucas Kreger-Stickles, University of Washington
Mark Oskin, University of Washington
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Leyla Nazhandali, University of Michigan
Bo Zhai, University of Michigan
Ryan Helfand, University of Michigan
Michael Minuth, University of Michigan
Javin Olson, University of Michigan
Sanjay Pant, University of Michigan
Anna Reeves, University of Michigan
Todd Austin, University of Michigan
David Blaauw, University of Michigan
An Ultra Low Power System Architecture for Sensor Network Applications
(slides)
Mark Hempstead, Harvard University
Nikhil Tripathi, Harvard University
Patrick Mauro, Harvard University
Gu-Yeon Wei, Harvard University
David Brooks, Harvard University
SESSION 4B: COHERENCE
Chair: Steven Reinhardt, University of Michigan, Ann Arbor
Temporal Streaming of Shared Memory
(slides)
Thomas F. Wenisch, Carnegie Mellon University
Stephen Somogyi, Carnegie Mellon University
Nikolaos Hardavellas, Carnegie Mellon University
Jangwoo Kim, Carnegie Mellon University
Anastassia Ailamaki, Carnegie Mellon University
Babak Falsafi, Carnegie Mellon University
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
(slides)
Andreas Moshovos, University of Toronto
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
(slides)
Jason F. Cantin, UW-Madison
Mikko H. Lipasti, UW-Madison
James E. Smith, UW-Madison
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| 10:30-11:00 | Break (Capitol Promenade) |
| 11:00-12:30 |
SESSION 5A: APPLYING COMPILERS & DEBUGGING SUPPORT
Chair: Susan Eggers, University of Washington
Improving Program Efficiency by Packing Instructions into Registers
(slides)
Stephen Hines, Florida State University
Joshua Green, Florida State University
Gary Tyson, Florida State University
David Whalley, Florida State University
An Architecture Framework for Transparent Instruction Set Customization in
Embedded Processors
(slides)
Nathan Clark, University of Michigan
Jason Blome, University of Michigan
Michael Chu, University of Michigan
Scott Mahlke, University of Michigan
Stuart Biles, ARM Ltd.
Krisztian Flautner, ARM Ltd.
BugNet: Continuously Recording Program Execution for Deterministic Replay
Debugging
(slides)
Satish Narayanasamy, UC San Diego
Gilles Pokam, UC San Diego
Brad Calder, UC San Diego
SESSION 5B: POWER
Chair: Uri Weiser, Intel
Mitigating Amdahl's Law Through EPI Throttling
(slides)
Murali Annavaram, Microarchitecture Research Lab, Intel Corporation
Ed Grochowski, Microarchitecture Research Lab, Intel Corporation
John Shen, Microarchitecture Research Lab, Intel Corporation
Increased Scalability and Power Efficiency by Using Multiple Speed
Pipelines
(slides)
Emil Talpes, Carnegie Mellon University
Diana Marculescu, Carnegie Mellon University
Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection
(slides)
Vlad Petric, University of Pennsylvania
Amir Roth, University of Pennsylvania
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| 12:30-1:45 | Lunch (Grand Terrace)
Generous corporate support provided by AMD
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| 1:45-2:30 | Awards Presentation (Ballroom A&B)
Most Influential Paper Award for papers presented in 1990: Norman P. Jouppi
(slides)
Maurice Wilkes Award: Steven L. Scott (Wolfe did not use slides)
Eckert-Mauchly Award: Robert P. Colwell
(slides)
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| 2:30-4:00 |
(Due to logistical requirements, the panel now precedes Sessions 6A/6B.)
Panel: Chip Multiprocessors (CMPs) are here, but where are the threads?
Organizer: Babak Falsafi, Carnegie Mellon University
(slides)
Maurice Herlihy, Brown University (slides)
Wen-Mei Hwu, University of Ilinois (slides)
Todd Mowry, Intel Research Pittsburgh/Carnegie Mellon University (slides)
Gurindar Sohi, University of Wisconsin (slides)
Marc Tremblay, Sun Microsystems (slides)
Michael Wolfe, The Portland Group (Wolfe did not use slides)
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| 4:00-4:30 | Break (Capitol Promenade) |
| 4:30-6:00 |
SESSION 6A: CHIP MULTIPROCESSOR MEMORY HIERARCHIES
Chair: Joel Emer, Intel
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip
Multiprocessors
(slides)
Michael Zhang, MIT
Krste Asanovic, MIT
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip
Multiprocessors
(slides)
Evan Speight, IBM Austin Research Lab
Hazim Shafi, IBM Austin Research Lab
Lixin Zhang, IBM Austin Research Lab
Ram Rajamony, IBM Austin Research Lab
Optimizing Replication, Communication, and Capacity Allocation in CMPs
(slides)
Zeshan Chishti, Purdue University
Michael D. Powell, Purdue University
T. N. Vijaykumar, Purdue University
SESSION 6B: RUNAHEAD & BRANCH PREDICTION
Chair: Sanjay Patel, University of Illinois, Urbana-Champaign
Techniques for Efficient Processing in Runahead Execution Engines
(slides)
Onur Mutlu, University of Texas at Austin
Hyesoon Kim, University of Texas at Austin
Yale N. Patt, University of Texas at Austin
Piecewise Linear Branch Prediction
Daniel A. Jiménez, Rutgers University
Analysis of the O-GEometric History Length Branch Predictor
(slides)
André Seznec, IRISA/INRIA/HIPEAC
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| 6:00-7:00 |
Business Meeting (Ballroom A) |
| 7:00-9:00 |
Conference Banquet (Rooftop, Center)
Generous corporate support provided by Cray
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| 9:00-??? |
Official Unofficial Nighttime Event
(Essen Haus) |
| 8:00-9:00 | Breakfast (Grand Terrace East) |
| 9:00-10:30 |
SESSION 7A: INTERCONNECTION NETWORKS
Chair: Steve Scott, Cray
Interconnections in Multi-Core Architectures: Understanding Mechanisms,
Overheads and Scaling
(slides)
Rakesh Kumar, UCSD
Victor Zyuban, IBM TJ Watson Research Center
Dean M. Tullsen, UCSD
Microarchitecture of a High-Radix Router
(slides)
John Kim, Stanford University
William Dally, Stanford University
Brian Towles, D. E. Shaw Research and Development
Amit Gupta, Stanford University
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh
Networks
(slides)
DaeHo Seo, Purdue University
Akif Ali, Purdue University
Won-Taek Lim, Purdue University
Nauman Rafique, Purdue University
Mithuna Thottethodi, Purdue University
SESSION 7B: LOAD & STORE QUEUES
Chair: Mateo Valero, UP Catalunya
Scalable Load and Store Processing in Latency Tolerant Processors
(slides)
Amit Gandhi, Portland State University
Haitham Akkary, Intel
Ravi Rajwar, Intel
Srikanth T. Srinivasan, Intel
Konrad Lai, Intel
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load
Optimization
(slides)
Amir Roth, University of Pennsylvania
Store Buffer Design in First-Level Multibanked Data Caches
(slides)
Enrique F. Torres, Universidad de Zaragoza / HiPEAC
Pablo Ibañez, Universidad de Zaragoza / HiPEAC
Victor Viñals, Universidad de Zaragoza / HiPEAC
Jose Maria Llabería, Universidad Politècnica de Catalunya
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| 10:30-11:00 | Break (Grand Terrace East) |
| 11:00-12:30 |
SESSION 8A: MULTIPROCESSOR ISSUES
Chair: Christos Kozyrakis, Stanford University
Dynamic Verification of Sequential Consistency
(slides)
Albert Meixner, Duke University
Daniel J. Sorin, Duke University
Virtualizing Transactional Memory
Ravi Rajwar, Intel
Maurice Herlihy, Brown
Konrad Lai, Intel
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Saisanthosh Balakrishnan, University of Wisconsin-Madison
Ravi Rajwar, Intel
Mike Upton, Intel
Konrad Lai, Intel
SESSION 8B: RELIABILITY & A CACHE ORGANIZATION
Chair: Steve Keckler, University of Texas, Austin
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Jayanth Srinivasan, University of Illinois, Urbana-Champaign
Sarita V. Adve, University of Illinois, Urbana-Champaign
Pradip Bose, IBM T.J. Watson Research Center
Jude A. Rivers, IBM T.J. Watson Research Center
Computing Architectural Vulnerability Factors for Address-Based
Structures
(slides)
Arijit Biswas, Intel
Raz Cheveresan, Sun Microsystems
Joel Emer, Intel
Shubhendu S. Mukherjee, Intel
Paul Racunas, Intel
Ram Rangan, Princeton
The V-Way Cache: Demand Based Associativity via Global Replacement
(slides)
Moinuddin K. Qureshi, The University of Texas at Austin
David Thompson, The University of Texas at Austin
Yale N. Patt, The University of Texas at Austin
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