Disclaimer
These are notes I made from papers in the reading list. At times I might have included screenshots of pictures. Please shoot me an email if you want that taken down : though you can download free copy of almost all of these papers (scholar.google.com). Also its all my take on the papers, depends on my mood, level of understanding, etc., These are not reviews, just points I thought were important.
Feel free to copy.
Uploaded : Feb 2012

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(2.1.1) Implementing Precise Interrupts in Pipelined Processors
(2.1.2) ILP History, Overview and Prespective
(2.1.3) Branch Predictor
(2.1.4) Multiscalar Processors
(2.1.5) complexity effective superscalar processors
(2.1.6) Dynamic speculation and syn of Data Dependencies
(2.1.7) Continual Flow Pipelines
(2.2.1) Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy
(2.2.2) Virtual memory
(2.2.3) Contemporary DRAM architectures
(2.2.4) Non Uniform Cache structure
(2.2.5) A Perfect Taxonomy
(2.3.2) MIT Tagged token
(2.3.3) Compiler Technology for Future Microprocessors
(2.3.4) IA64
(2.3.5) ARM ISA
(2.4.1) Cray 1
(2.4.2) MIPS R10000
(2.4.3) IBM G5
(2.5.1) Power : First class design constraint
(2.5.2) Optimizing pipelines for Power and Performance
(2.5.3) Razor
(2.5.4) Shekar Borkar Transistor variability
(2.5.5) EDGE architecture (TRIPS)
(2.5.6) Cosmic rays
(2.5.7) 3D die-stacking
(2.5.8) NAND Flash
(3.1.1) Data parallel Algos
(3.1.2) Algorithms for scalable syncronization
(3.1.3) SPLASH-2
(3.1.4) OpenMP
(3.1.5) Variability in Architectural simulation
(3.2.1) Lamport
(3.2.2) Cache Invalidation patterns
(3.2.3) ~ Consistency models
(3.2.4) Victim Replication
(3.2.5) Token Coherence
(3.3.1) T3E
(3.3.2) SGI Origin
(3.3.3) Wildfire : Scalable SMPs
(3.3.4) Piranha
(3.3.5) Niagara 32 way SPARC
(3.3.6) nVidia Tesla
(3.4.1) CM-5
(3.4.2) Route Packets, Not Wires: On-Chip Interconnection Networks
(3.4.3) alpha 21364 network architecture
(3.4.4) Butterfly OCN
(3.5.1) Thread Level Speculation
(3.5.2) Speculative Lock Elision
(3.5.3) LogTM
(3.5.4) Store-wait-free MuP
(3.6.1) IF and Issue on a SMT
(3.6.2) Amdhal's law in the multicore era