CS/ECE 755: VLSI Systems Design

Spring 2002 Offering


Prof. David Wood


Pranay Koka

Table of Contents

What's New in Class

Course Information

Course Goals

Course Contents:

In this course we will study the design of digital systems using MOS circuits, with an emphasis on architectural and micro-architectural trade-offs. We will treat the subject as a natural outgrowth of digitial system architecture, and will not assume any background in semiconductor devices. This course will have a different emphasis than when it is taught by the ECE faculty. When taught in ECE, the course emphasizes circuit design, circuit optimization, and CAD algorithms. In this course, we will touch on each of these areas, but spend more time focusing on the architectural aspects of VLSI systems design. We will examine the impact of VLSI technology on contemporary processor and memory system designs.

This is NOT a circuits course

CAD Tools and Computers:

We will be using the Mentor Graphics CAD tools. These are extremely powerful commercial tools. However, they have a "large learning curve," and we anticipate some problems. Students should take this into account when starting individual assignments and their project. There will be considerable leeway granted if there are widespread problems with the tools, however, failing to leave sufficient time before the due date is not a valid excuse. The computers assigned for the course are the color Suns in the Computer Sciences Instruction labs (e.g., Room 1358, 1368, and 1347/1349 CSS). If you are not familiar with UNIX, you should attend one of the UNIX orientation sessions given during the first two weeks of classes.

ECE students will also have accounts on the CAE machines. Most of the tools will be available at CAE, although there may be minor differences in the configurations. We will try to minimize these as much as possible.

Although the details of the design tools will not be covered in class, the TA will organize several additional recitation sections to help you learn them.

Course Requirements:

Course Grading:

Tentative Schedule:

Week Dates Topics (Approximate)
1 1/23-1/25 Overview, MOS as an Abstract Technology, CAD
2 1/28-2/1  MOS Transistors and Gates, Delay Estimation
3 2/4-2/8 Simulation, Processing
4 2/11-2/15 Topology, PLAs, Catchup
5 2/18-2/22 Sequential logic, Datapaths 
6 2/25-3/1 Arithmetic, Testing
7 3/4-3/8 Review, Midterm
- 3/11-3/15 Spring Break
8 3/18-3/22 Processors
9 3/25-3/29 Processors
10 4/1-4/5 Memory Designs
11 4/8-4/12 Memory Designs
12 4/15-4/19 Billion Transistor Chips
13 4/22-4/26 Low Power Design
14 4/29-5/3 Review
15 5/6-5/10 Project Presentations
- 5/17 Final Exam, 2:45pm

Text and Reader

Lecture Notes



Spring 2002 Project

General project information

Projects from prior years

Tutorials on CAD Tools

Spring 2002 tutorials:

Spring 2001 tutorials:

  1. Beginning Tutorials
  2. Creating Automatic Generated Layout from a HDL file
  3. Creating Automatic Generated Layout from a Schematic
  4. Creating Full-custom Layout
  5. Miscellaneous

Spring 2000 tutorials:

Spring 1999 tutorials:

Supporting Material for the CAD Tools

Discussion Sessions

Spring 2001's discussions:

Spring 2000's discussions:

Spring 1999's discussions:

Course E-mail Archives

Past Exams