- b -

• BackingStoreEntry() : BackingStoreEntry
• BadClient() : BaseRemoteGDB::BadClient
• BadDevice() : BadDevice
• Bank() : DRAMCtrl::Bank
• BankedArray() : BankedArray
• BankedRegs() : Pl390::BankedRegs
• BareIronMipsSystem() : BareIronMipsSystem
• Barrier() : Barrier , HsailISA::Barrier
• BarrierDataRequest() : Minor::LSQ::BarrierDataRequest
• BarrierEvent() : BaseGlobalEvent::BarrierEvent , GlobalEvent::BarrierEvent , GlobalSyncEvent::BarrierEvent
• base() : MipsISA::MipsFaultBase
• Base() : Sinic::Base
• BaseArmKvmCPU() : BaseArmKvmCPU
• BaseBufferArg() : BaseBufferArg
• BaseCache() : BaseCache
• baseCheck() : Stats::Info
• BaseConfigEntry() : X86ISA::IntelMP::BaseConfigEntry
• BaseDynInst() : BaseDynInst< Impl >
• BaseGdbRegCache() : BaseRemoteGDB::BaseGdbRegCache
• BaseGen() : BaseGen
• BaseGic() : BaseGic
• BaseGlobalEvent() : BaseGlobalEvent
• BaseGlobalEventTemplate() : BaseGlobalEventTemplate< Derived >
• BaseISADevice() : ArmISA::BaseISADevice
• BaseKvmCPU() : BaseKvmCPU
• BaseKvmTimer() : BaseKvmTimer
• BaseMasterPort() : BaseMasterPort
• BaseMemProbe() : BaseMemProbe
• BaseO3CPU() : BaseO3CPU
• BaseO3DynInst() : BaseO3DynInst< Impl >
• BaseOperand() : BaseOperand
• BasePixelPump() : BasePixelPump
• BasePrefetcher() : BasePrefetcher
• BaseRemoteGDB() : BaseRemoteGDB
• BaseSetAssoc() : BaseSetAssoc
• BaseSimpleCPU() : BaseSimpleCPU
• BaseSlavePort() : BaseSlavePort
• BaseTags() : BaseTags
• BaseTagsCallback() : BaseTagsCallback
• BaseTagsDumpCallback() : BaseTagsDumpCallback
• BaseTLB() : BaseTLB
• baseUpdate() : LTAGE
• BaseXBar() : BaseXBar
• BasicBlock() : BasicBlock
• basicBlock() : ControlFlowInfo
• BasicExtLink() : BasicExtLink
• BasicIntLink() : BasicIntLink
• BasicLink() : BasicLink
• BasicPioDevice() : BasicPioDevice
• BasicRouter() : BasicRouter
• BasicSignal() : BasicSignal
• begin() : AddrRangeMap< V > , PacketFifo , SparcISA::TlbMap , Stats::Output , Stats::Text
• beginLine() : BasePixelPump
• bias() : ElfObject , ObjectFile
• BigFpMemImmOp() : ArmISA::BigFpMemImmOp
• BigFpMemLitOp() : ArmISA::BigFpMemLitOp
• BigFpMemPostOp() : ArmISA::BigFpMemPostOp
• BigFpMemPreOp() : ArmISA::BigFpMemPreOp
• BigFpMemRegOp() : ArmISA::BigFpMemRegOp
• BimodalEntry() : LTAGE::BimodalEntry
• BiModeBP() : BiModeBP
• BinaryNode() : Stats::BinaryNode< Op >
• binaryOp() : ArmISA::FpOp
• bind() : BaseMasterPort , MasterPort , SlavePort
• bindAllPorts() : CxxConfigManager
• bindex() : LTAGE
• bindList() : OFSchedulingPolicy , RRSchedulingPolicy , Scheduler , SchedulingPolicy< Impl >
• bindMasterPort() : CxxConfigManager
• bindObjectPorts() : CxxConfigManager
• bindPort() : CxxConfigManager
• bindWaveList() : FetchUnit
• BiosInformation() : X86ISA::SMBios::BiosInformation
• bitIndex() : NetDest
• Bitmap() : Bitmap
• BitUnion32() : ArchTimer , ArmISA::PMU , CpuLocalTimer::Timer , HDLcd , Pl390 , RealViewCtrl , Sp804::Timer , VGic , X86ISA::Interrupts , X86ISA::PageFault
• BitUnion64() : X86ISA::I82094AA
• BitUnion8() : IdeController , Intel8254Timer , MC146818 , Pl050 , Pl111 , VirtIODeviceBase , X86ISA::I8042 , X86ISA::PS2Mouse , X86ISA::Speaker
• BitUnionOperators() : BitfieldBackend::BitUnionOperators< Type, Base >
• blkAlign() : BaseTags
• block() : DefaultDecode< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• blockAddress() : BasePrefetcher
• blockAlign() : MemTest
• BlockBloomFilter() : BlockBloomFilter
• blockIndex() : BasePrefetcher
• blockMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• blockOnQueue() : AbstractController
• BoundRange() : X86ISA::BoundRange
• BPredUnit() : BPredUnit
• BranchCond() : PowerISA::BranchCond
• branchCount() : DefaultFetch< Impl >
• BranchData() : Minor::BranchData
• BranchEret64() : ArmISA::BranchEret64
• BranchImm() : ArmISA::BranchImm
• BranchImm64() : ArmISA::BranchImm64
• BranchImmCond() : ArmISA::BranchImmCond
• BranchImmCond64() : ArmISA::BranchImmCond64
• BranchImmImmReg64() : ArmISA::BranchImmImmReg64
• BranchImmReg() : ArmISA::BranchImmReg
• BranchImmReg64() : ArmISA::BranchImmReg64
• BranchInfo() : LTAGE::BranchInfo
• branching() : GenericISA::DelaySlotPCState< MachInst > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::SimplePCState< MachInst > , GenericISA::UPCState< MachInst > , X86ISA::PCState
• BranchNonPCRel() : PowerISA::BranchNonPCRel
• BranchNonPCRelCond() : PowerISA::BranchNonPCRelCond
• BranchPCRel() : PowerISA::BranchPCRel
• BranchPCRelCond() : PowerISA::BranchPCRelCond
• BranchReg() : ArmISA::BranchReg
• BranchReg64() : ArmISA::BranchReg64
• BranchRegCond() : ArmISA::BranchRegCond , PowerISA::BranchRegCond
• BranchRegReg() : ArmISA::BranchRegReg
• BranchRet64() : ArmISA::BranchRet64
• branchTarget() : ArmISA::BranchImm64 , ArmISA::BranchImmImmReg64 , ArmISA::BranchImmReg64 , BaseDynInst< Impl > , PowerISA::BranchNonPCRel , PowerISA::BranchNonPCRelCond , PowerISA::BranchPCRel , PowerISA::BranchPCRelCond , PowerISA::BranchRegCond , StaticInst
• BrDirectInst() : HsailISA::BrDirectInst
• break_type() : BaseRemoteGDB
• BreakPCEvent() : BreakPCEvent
• breakpoint() : BaseRemoteGDB , MipsSystem , RiscvSystem , System
• Breakpoint() : X86ISA::Breakpoint
• BreakpointFault() : RiscvISA::BreakpointFault
• Bridge() : Bridge
• BridgeMasterPort() : Bridge::BridgeMasterPort
• BridgeSlavePort() : Bridge::BridgeSlavePort
• BrigObject() : BrigObject
• BrigRegOperandInfo() : BrigRegOperandInfo
• BrIndirectInst() : HsailISA::BrIndirectInst
• BrInstBase() : HsailISA::BrInstBase< TargetType >
• BrnDirectInst() : HsailISA::BrnDirectInst
• BrnIndirectInst() : HsailISA::BrnIndirectInst
• BrnInstBase() : HsailISA::BrnInstBase< TargetType >
• broadcast() : Net::EthAddr , NetDest , Set
• bssBase() : ObjectFile
• bssSize() : ObjectFile
• BTBEntry() : DefaultBTB::BTBEntry
• BTBLookup() : BPredUnit
• btbUpdate() : BiModeBP , BPredUnit
• BTBUpdate() : BPredUnit
• btbUpdate() : LocalBP , LTAGE , TournamentBP
• BTBValid() : BPredUnit
• bubble() : Minor::BranchData , Minor::BubbleTraitsAdaptor< ElemType > , Minor::BubbleTraitsPtrAdaptor< PtrType, ElemType > , Minor::ForwardLineData , Minor::MinorDynInst , Minor::NoBubbleTraits< ElemType > , Minor::QueuedInst
• bubbleFill() : Minor::ForwardInstData
• BufferArg() : BufferArg
• bufferData() : X86ISA::PS2Device
• bufferPtr() : BufferArg
• bufLen() : iGbReg::Regs::SRRCTL
• buildInst() : DefaultFetch< Impl >
• buildPacket() : TimingSimpleCPU
• buildSplitPacket() : TimingSimpleCPU
• BulkBloomFilter() : BulkBloomFilter
• burstAlign() : DRAMCtrl
• BurstHelper() : DRAMCtrl::BurstHelper
• burstSize() : DRAMSim2Wrapper
• Bus() : X86ISA::IntelMP::Bus
• busAddr() : PciDevice
• BusHierarchy() : X86ISA::IntelMP::BusHierarchy
• busy() : DistEtherLink::Link , DMASequencer , EtherBus , EtherLink::Link , Shader
• bypassCaches() : System
• bytes() : Net::EthAddr , Net::EthHdr , Net::Ip6Hdr , Net::IpHdr , Net::TcpHdr , Net::TcpOpt , Net::UdpHdr
• ByteTracker() : MemChecker::ByteTracker