- t -

• T1000() : T1000
• TableWalker() : ArmISA::TableWalker
• tadvProcess() : IGbE
• tag() : AtagCmdline , AtagCore , AtagHeader , AtagMem , AtagNone , AtagRev , AtagSerial
• TageEntry() : LTAGE::TageEntry
• TaggedPrefetcher() : TaggedPrefetcher
• TagRead() : SparcISA::TLB
• takeInt() : ArmISA::Interrupts
• takeInterrupt() : Minor::Execute
• takeOverFrom() : AlphaISA::Decoder , AlphaISA::TLB , ArmISA::Decoder , ArmISA::TLB , AtomicSimpleCPU , BaseKvmCPU , BaseTLB , Checker< Impl > , CheckerThreadContext< TC > , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , FUPool , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , MinorCPU , MipsISA::Decoder , MipsISA::TLB , O3ThreadContext< class > , PowerISA::Decoder , PowerISA::TLB , ProxyThreadContext< TC > , RiscvISA::Decoder , RiscvISA::TLB , ROB< Impl > , SimpleThread , SparcISA::Decoder , SparcISA::TLB , ThreadContext , TimingSimpleCPU , TraceCPU , X86ISA::Decoder , X86ISA::TLB
• TapEvent() : TapEvent
• TapListener() : TapListener
• Target() : MSHR::Target , WriteQueueEntry::Target
• TargetList() : MSHR::TargetList , WriteQueueEntry::TargetList
• task() : AlphaISA::ProcessInfo , ArmISA::ProcessInfo , MipsISA::ProcessInfo , PowerISA::ProcessInfo , RiscvISA::ProcessInfo , X86ISA::ProcessInfo
• taskHandler() : UFSHostDevice
• taskId() : Request
• taskStart() : UFSHostDevice
• TBETable() : TBETable< ENTRY >
• tcBase() : BaseDynInst< Impl > , CheckerCPU , ExecContext , FullO3CPU< Impl > , Minor::ExecContext , SimpleExecContext
• TCPIface() : TCPIface
• TcpPtr() : Net::TcpPtr
• Temp() : Stats::Temp
• Terminal() : Terminal
• TermRecvQueue() : VirtIOConsole::TermRecvQueue
• TermTransQueue() : VirtIOConsole::TermTransQueue
• ternaryOp() : ArmISA::FpOp
• test() : WriteMask
• testCacheAccess() : CacheMemory
• testCmdAttrib() : MemCmd
• testDrainComplete() : RubyPort
• testTranslation() : ArmISA::TLB
• testWalk() : ArmISA::TableWalker , ArmISA::TLB
• texcb() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor
• Text() : Stats::Text
• textBase() : ObjectFile
• textSize() : ObjectFile
• tgid() : Process
• ThermalCapacitor() : ThermalCapacitor
• ThermalDomain() : ThermalDomain
• ThermalModel() : ThermalModel
• ThermalNode() : ThermalNode
• ThermalProbeListener() : PowerModel::ThermalProbeListener
• ThermalReference() : ThermalReference
• ThermalResistor() : ThermalResistor
• thermalUpdateCallback() : PowerModel
• threadBase() : CheckerCPU
• threadId() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• ThreadInfo() : FreeBSD::ThreadInfo , IndirectPredictor::ThreadInfo , Linux::ThreadInfo
• threadSnoop() : AtomicSimpleCPU , Minor::LSQ , TimingSimpleCPU
• ThreadState() : ThreadState , Trace::ArmNativeTrace::ThreadState
• ThreeNonUniformSourceInst() : HsailISA::ThreeNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType, Src2DataType >
• ThreeNonUniformSourceInstBase() : HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType >
• Throttle() : Throttle
• thumbPcElrOffset() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T >
• thumbPcOffset() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T >
• tick() : AtomicSimpleCPU , BaseKvmCPU , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DRAMSim2 , DRAMSim2Wrapper , FullO3CPU< Impl > , GarnetSyntheticTraffic , IGbE , LSQ< Impl > , LSQUnit< Impl > , MemTest
• tickClock() : MC146818
• tickDelta() : TraceCPU::FixedRetryGen
• Ticked() : Ticked
• TickedObject() : TickedObject
• TickEvent() : AtomicSimpleCPU::TickEvent , BaseKvmCPU::TickEvent , FullO3CPU< Impl >::TickEvent , GarnetSyntheticTraffic::TickEvent , GpuDispatcher::TickEvent , LdsState::TickEvent , Shader::TickEvent , TimingSimpleCPU::TimingCPUPort::TickEvent
• ticks() : Shader , TLBCoalescer , X86ISA::GpuTLB
• ticksFromHostCycles() : BaseKvmTimer
• ticksFromHostNs() : BaseKvmTimer
• ticksToCycles() : Clocked
• ticksTokHz() : EnergyCtrl
• tickToCycles() : Shader , TLBCoalescer , X86ISA::GpuTLB
• tidvProcess() : IGbE
• time() : Request
• Time() : Time
• time() : Time
• TimeBuffer() : TimeBuffer< T >
• Timer() : CpuLocalTimer::Timer , Sp804::Timer
• timerAtZero() : CpuLocalTimer::Timer
• timerRead() : GenericTimerMem
• TimerTable() : TimerTable
• timerValue() : ArchTimer
• timerWrite() : GenericTimerMem
• timeSync() : Root
• timeSyncEnable() : Root
• timeSyncEnabled() : Root
• timeSyncPeriod() : Root
• timeSyncSpinThreshold() : Root
• TimingCPUPort() : TimingSimpleCPU::TimingCPUPort
• TimingExpr() : TimingExpr
• TimingExprBin() : TimingExprBin
• TimingExprEvalContext() : TimingExprEvalContext
• TimingExprIf() : TimingExprIf
• TimingExprLet() : TimingExprLet
• TimingExprLiteral() : TimingExprLiteral
• TimingExprReadIntReg() : TimingExprReadIntReg
• TimingExprRef() : TimingExprRef
• TimingExprSrcReg() : TimingExprSrcReg
• TimingExprUn() : TimingExprUn
• timings() : BasePixelPump
• TimingSimpleCPU() : TimingSimpleCPU
• TLB() : AlphaISA::TLB , ArmISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB , X86ISA::TLB
• TLBCoalescer() : TLBCoalescer
• TlbEntry() : AlphaISA::TlbEntry , ArmISA::TlbEntry , MipsISA::TlbEntry , PowerISA::TlbEntry , RiscvISA::TlbEntry , SparcISA::TlbEntry
• TLBEvent() : X86ISA::GpuTLB::TLBEvent
• TlbFault() : MipsISA::TlbFault< T >
• tlbiALL() : ArmISA::ISA
• tlbiALLN() : ArmISA::ISA
• tlbiMVA() : ArmISA::ISA
• TlbInvalidFault() : MipsISA::TlbInvalidFault
• tlbiVA() : ArmISA::ISA
• tlbLookup() : X86ISA::GpuTLB
• TlbModifiedFault() : MipsISA::TlbModifiedFault
• TLBPort() : GpuDispatcher::TLBPort
• TlbRefillFault() : MipsISA::TlbRefillFault
• TlbTestInterface() : ArmISA::TlbTestInterface
• to_string() : AddrRange
• toggleSync() : DistIface
• toInt() : MemCmd
• toLookupLevel() : ArmISA::TableWalker
• toMicroVolt() : EnergyCtrl
• top() : ReturnAddrStack
• topIdx() : ReturnAddrStack
• toPixel() : PixelConverter::Channel , PixelConverter
• Topology() : Topology
• tos() : Net::IpHdr
• toStr() : LinearEquation , LinearSystem , MathExpr::Node , MathExpr
• toString() : MemCmd
• total() : Stats::BinaryNode< Op > , Stats::ConstNode< T > , Stats::ConstVectorNode< T > , Stats::Formula , Stats::FormulaInfoProxy< Stat > , Stats::FormulaNode , Stats::FunctorProxy< T > , Stats::MethodProxy< T, V > , Stats::Node , Stats::ScalarBase< Derived, Stor > , Stats::ScalarInfo , Stats::ScalarInfoProxy< Stat > , Stats::ScalarProxyNode< Stat > , Stats::ScalarStatNode , Stats::SumNode< Op > , Stats::UnaryNode< Op > , Stats::ValueBase< Derived > , Stats::ValueProxy< T > , Stats::Vector2dBase< Derived, Stor > , Stats::Vector2dInfo , Stats::Vector2dInfoProxy< Stat > , Stats::VectorBase< Derived, Stor > , Stats::VectorInfo , Stats::VectorInfoProxy< Stat > , Stats::VectorProxy< Stat > , Stats::VectorStatNode
• totalInsts() : BaseKvmCPU , BaseSimpleCPU , CheckerCPU , FullO3CPU< Impl > , MinorCPU , TraceCPU
• totalNumPhysRegs() : PhysRegFile
• totalOps() : BaseKvmCPU , BaseSimpleCPU , CheckerCPU , FullO3CPU< Impl > , MinorCPU , TraceCPU
• totalSize() : PhysicalMemory
• totalSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• touch() : AbstractReplacementPolicy , LRUPolicy , PseudoLRUPolicy , WeightedLRUPolicy
• TournamentBP() : TournamentBP
• tr() : Net::IpOpt
• trace() : AlphaISA::StackTrace , ArmISA::StackTrace , Event , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , SparcISA::StackTrace , X86ISA::StackTrace
• traceCommit() : SimpleTrace
• TraceCPU() : TraceCPU
• traceFetch() : SimpleTrace
• TraceGen() : TraceGen
• TraceInfo() : ElasticTrace::TraceInfo
• traceInst() : Trace::ExeTracerRecord , Trace::InstPBTrace
• traceMem() : Trace::InstPBTrace
• trackLoadLocked() : AbstractMemory , CacheBlk
• TrafficGen() : TrafficGen
• TrafficGenPort() : TrafficGen::TrafficGenPort
• Transaction() : MemChecker::Transaction
• transferDone() : NSGigE , Sinic::Device , UFSHostDevice
• transferHandler() : UFSHostDevice
• transferStart() : UFSHostDevice
• transition() : TrafficGen
• translate() : PageTableBase , SparcISA::PageTableEntry , X86ISA::GpuTLB , X86ISA::TLB
• translateAtomic() : AlphaISA::TLB , ArmISA::TLB , GenericTLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB , X86ISA::GpuTLB , X86ISA::TLB
• translateComplete() : ArmISA::TLB
• translateData() : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB
• translateFs() : ArmISA::TLB
• translateFunctional() : AlphaISA::TLB , ArmISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB , X86ISA::TLB
• translateInst() : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB
• translateInt() : X86ISA::GpuTLB , X86ISA::TLB
• transLatency() : DVFSHandler
• translateSe() : ArmISA::TLB
• translateTiming() : AlphaISA::TLB , ArmISA::Stage2MMU::Stage2Translation , ArmISA::TLB , GenericTLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SparcISA::TLB , X86ISA::GpuTLB , X86ISA::TLB
• translationCheck() : ArmISA::TlbTestInterface
• translationCompleted() : BaseDynInst< Impl >
• TranslationEvent() : Minor::LSQ::SplitDataRequest::TranslationEvent
• translationFault() : TimingSimpleCPU
• translationReturn() : X86ISA::GpuTLB
• translationStarted() : BaseDynInst< Impl >
• TranslationState() : X86ISA::GpuTLB::TranslationState
• transmit() : DistEtherLink::TxLink , EtherLink::Link , EtherSwitch::Interface , NSGigE , Sinic::Device
• trap() : BaseO3DynInst< Impl > , BaseRemoteGDB , FullO3CPU< Impl >
• TrapEvent() : BaseRemoteGDB::TrapEvent , DefaultCommit< Impl >::TrapEvent
• TrapInstruction() : SparcISA::TrapInstruction
• trapType() : SparcISA::EnumeratedFault< T > , SparcISA::SparcFault< T > , SparcISA::SparcFaultBase
• trickBoxCheck() : ArmISA::TLB
• Trie() : Trie< Key, Value >
• triggerTimerInterrupt() : X86ISA::Interrupts
• tryAccess() : BankedArray
• tryCacheAccess() : CacheMemory , GPUCoalescer
• tryCompleteDrain() : AtomicSimpleCPU , TimingSimpleCPU
• tryDrain() : BaseKvmCPU , DrainManager , FullO3CPU< Impl >
• tryEval() : MathExprPowerModel
• tryFile() : AoutObject , BrigObject , DtbObject , EcoffObject , ElfObject , RawObject
• tryGet() : DmaReadFifo
• tryGetRegList() : BaseArmKvmCPU
• tryMemsetBlob() : SETranslatingPortProxy
• tryNext() : TraceCPU::FixedRetryGen
• tryPCEvents() : Minor::Execute
• tryReadBlob() : SETranslatingPortProxy
• tryReadString() : SETranslatingPortProxy
• trySend() : VirtIOConsole::TermRecvQueue
• trySendRetries() : RubyPort
• trySendTiming() : Bridge::BridgeMasterPort , Bridge::BridgeSlavePort , SerialLink::SerialLinkMasterPort , SerialLink::SerialLinkSlavePort
• trySendTimingReq() : DmaPort
• tryTiming() : BaseXBar::Layer< SrcType, DstType >
• tryToBranch() : Minor::Execute
• tryToSend() : Minor::Fetch1 , Minor::LSQ
• tryToSendToTransfers() : Minor::Fetch1 , Minor::LSQ
• tryWriteBlob() : SETranslatingPortProxy
• tryWriteString() : SETranslatingPortProxy
• ts() : Net::IpOpt
• tsecr() : Net::TcpOpt
• Tsunami() : Tsunami
• TsunamiCChip() : TsunamiCChip
• TsunamiIO() : TsunamiIO
• TsunamiPChip() : TsunamiPChip
• tsval() : Net::TcpOpt
• TteRead() : SparcISA::TLB
• TteTag() : SparcISA::TteTag
• ttl() : Net::IpHdr
• TwoNonUniformSourceInst() : HsailISA::TwoNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType >
• TwoNonUniformSourceInstBase() : HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType >
• txComplete() : EtherLink::Link
• TxDescCache() : IGbE::TxDescCache
• txDmaDone() : Sinic::Device
• txDmaReadDone() : NSGigE
• txDmaWriteDone() : NSGigE
• txDone() : DistEtherLink::TxLink , EtherBus , EtherLink::Link
• txDump() : NSGigE , Sinic::Device
• TxEvent() : EtherTapBase::TxEvent
• txEventTransmit() : NSGigE , Sinic::Device
• txKick() : NSGigE , Sinic::Device
• TxLink() : DistEtherLink::TxLink
• txReset() : NSGigE
• txStateMachine() : IGbE
• txWire() : IGbE
• type() : ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::LongDescriptor , BaseRemoteGDB::TrapEvent , Net::EthHdr , Net::IpOpt , Net::TcpOpt
• typeClass() : Net::IpOpt
• typeCopied() : Net::IpOpt
• TypedBufferArg() : TypedBufferArg< T >
• typeNumber() : Net::IpOpt
• typeOfSmallest() : PersistentTable
• typeToStr() : ElasticTrace::TraceInfo , TraceCPU::ElasticDataGen::GraphNode