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• nack() : X86ISA::PS2Device
• name() : ActivityRecorder , AlphaISA::AlignmentFault , AlphaISA::ArithmeticFault , AlphaISA::DtbAcvFault , AlphaISA::DtbAlignmentFault , AlphaISA::DtbFault , AlphaISA::DtbPageFault , AlphaISA::FloatEnableFault , AlphaISA::IntegerOverflowFault , AlphaISA::InterruptFault , AlphaISA::ItbAcvFault , AlphaISA::ItbFault , AlphaISA::ItbPageFault , AlphaISA::MachineCheckFault , AlphaISA::NDtbMissFault , AlphaISA::PalFault , AlphaISA::PDtbMissFault , AlphaISA::ProcessInfo , AlphaISA::RemoteGDB::AlphaGdbRegCache , AlphaISA::ResetFault , AlphaISA::UnimplementedOpcodeFault , ArchTimer , ArmISA::ArmFaultVals< T > , ArmISA::ProcessInfo , ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ArmISA::TableWalker::WalkerState , BaseGen , BasePixelPump::PixelEvent , BaseRemoteGDB::BaseGdbRegCache , BaseRemoteGDB::HardBreakpoint , BaseRemoteGDB , BaseXBar::Layer< SrcType, DstType > , CallbackQueue , ConditionRegisterState , CopyEngine::CopyEngineChannel , CpuLocalTimer::Timer , Debug::Flag , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DistEtherLink::Link , DmaCallback , DRAMCtrl::Rank , ElasticTrace , EtherInt , EtherLink::Link , EtherSwitch::Interface::PortFifo , Event , EventQueue , EventWrapper< T, F > , ExecStage , FaultBase , FetchStage , GDBListener , GenericAlignmentFault , GenericISA::M5DebugFault , GenericPageTableFault , GlobalMemPipeline , HsaCode , HsaObject , IGbE::DescCache< T > , InstructionQueue< Impl > , Intel8254Timer::Counter , Intel8254Timer , Kernel::Statistics , LocalMemPipeline , LSQ< Impl > , LSQUnit< Impl > , MC146818 , MemDepUnit< MemDepPred, Impl >::MemDepEntry , MemDepUnit< MemDepPred, Impl > , MipsISA::MipsFault< T > , MipsISA::ProcessInfo , MipsISA::RemoteGDB::MipsGdbRegCache , Named , OutputStream , PacketQueue , PageTableBase , PAL , PCEvent , PciHost::DeviceInterface , PerfectSwitch , PhysicalMemory , Pl111 , Port , PowerISA::PowerFault , PowerISA::ProcessInfo , PowerISA::RemoteGDB::PowerGdbRegCache , ReExec , ReqPacketQueue , RespPacketQueue , RiscvISA::ProcessInfo , RiscvISA::RemoteGDB::RiscvGdbRegCache , RiscvISA::RiscvFault , ROB< Impl > , ScheduleStage , Scoreboard , ScoreboardCheckStage , SimObject , SimpleThread , SimpleTrace , SnoopRespPacketQueue , Sp804::Timer , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , SparcISA::SparcFault< T > , Stats::DataWrap< Derived, InfoProxyType > , StridePrefetcher::PCTable , SyscallDesc , SyscallRetryFault , Throttle , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , UnifiedFreeList , UnimpFault , VecRegisterState , VirtIO9PBase::FSQueue , VirtIOBlock::RequestQueue , VirtIOConsole::TermRecvQueue , VirtIOConsole::TermTransQueue , X86ISA::ProcessInfo , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache , X86ISA::UnimpInstFault , X86ISA::Walker::WalkerState , X86ISA::X86FaultBase
• Named() : Named
• nameOut() : Serializable::ScopedCheckpointSection
• NativeTrace() : Trace::NativeTrace
• NativeTraceRecord() : Trace::NativeTraceRecord
• nbrOutstanding() : DRAMSim2
• NDtbMissFault() : AlphaISA::NDtbMissFault
• need_stage() : InputUnit , VirtualChannel
• needMoreBytes() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• needsResponse() : MemCmd , Packet
• needsRetry() : SyscallReturn
• needsToBeSentToStoreBuffer() : Minor::LSQ::LSQRequest
• needsToTick() : Minor::LSQ
• needsWritable() : MemCmd , MSHR , Packet
• needWarning() : SyscallDesc
• NetDest() : NetDest
• netmask() : Net::IpNetmask
• Network() : Network
• NetworkInterface() : NetworkInterface
• NetworkLink() : NetworkLink
• next() : ChunkGenerator , VirtDescriptor
• nextAddress() : TimerTable
• nextCycle() : Clocked
• nextDescAddr() : ArmISA::TableWalker::LongDescriptor
• nextExecute() : TraceCPU::FixedRetryGen
• nextGlbRdBus() : ComputeUnit
• nextIdxs() : ArmISA::VfpMacroOp
• nextInstAddr() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , DefaultCommit< Impl > , FullO3CPU< Impl > , GenericISA::PCStateBase , GPUStaticInst , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• nextIOState() : BaseKvmCPU::KVMCpuPort
• nextLocRdBus() : ComputeUnit
• nextMode() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T >
• nextnlu() : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• nextPacketTick() : BaseGen , IdleGen , LinearGen , RandomGen , TraceGen
• nextPixel() : BasePixelPump , HDLcd::PixelPump
• nextPrefetchReadyTime() : BasePrefetcher , QueuedPrefetcher
• nextQueueReadyTime() : Cache
• nextReadyTime() : Queue< Entry >
• nextSeq() : X86ISA::TLB
• nextTableAddr() : ArmISA::TableWalker::LongDescriptor
• nextTick() : EventQueue
• nextWalk() : ArmISA::TableWalker
• nnpc() : GenericISA::DelaySlotPCState< MachInst >
• NoArchPageTable() : NoArchPageTable
• Node() : MathExpr::Node , StackDistCalc::Node , Trie< Key, Value >::Node
• nofault() : SparcISA::PageTableEntry
• NoMaliGpu() : NoMaliGpu
• NoncoherentXBar() : NoncoherentXBar
• NoncoherentXBarMasterPort() : NoncoherentXBar::NoncoherentXBarMasterPort
• NoncoherentXBarSlavePort() : NoncoherentXBar::NoncoherentXBarSlavePort
• NonCountingBloomFilter() : NonCountingBloomFilter
• noneSet() : Flags< T >
• NonMaskableInterrupt() : X86ISA::NonMaskableInterrupt
• nonSpecInstReady() : MemDepUnit< MemDepPred, Impl >
• noOutput() : Stats::Text
• noProgress() : TrafficGen
• noRequest() : MemTest
• noResponse() : MemTest
• normalize() : CircleBuf< T >
• notify() : ArmISA::PMU::ProbeListener , BaseMemProbe::PacketListener , BasePrefetcher , PowerModel::ThermalProbeListener , ProbeListenerArg< T, Arg > , ProbeListenerArgBase< Arg > , ProbePointArg< T > , QueuedPrefetcher
• notifyFork() : BaseKvmCPU , CowDiskImage , Drainable , KvmVM , RawDiskImage
• notifyWgCompl() : GpuDispatcher
• npc() : GenericISA::SimplePCState< MachInst >
• nsec() : Time
• NSGigE() : NSGigE
• NSGigEInt() : NSGigEInt
• null() : AtagHeader , AtagNone
• nullCallback() : IGbE::TxDescCache
• numActiveThreads() : FullO3CPU< Impl >
• numCCDestRegs() : BaseDynInst< Impl > , StaticInst
• numCCPhysRegs() : PhysRegFile
• numContexts() : System
• numDestRegs() : BaseDynInst< Impl > , StaticInst
• numDomains() : DVFSHandler
• numDstRegOperands() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrDirectInst , HsailISA::BrIndirectInst , HsailISA::BrnDirectInst , HsailISA::BrnIndirectInst , HsailISA::Call , HsailISA::CbrDirectInst , HsailISA::CbrIndirectInst , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• numFloatPhysRegs() : PhysRegFile
• numFPDestRegs() : BaseDynInst< Impl > , StaticInst
• numFreeCCRegs() : UnifiedFreeList
• numFreeEntries() : InstructionQueue< Impl > , LSQ< Impl > , ROB< Impl > , SimpleRenameMap , UnifiedRenameMap
• numFreeFloatRegs() : UnifiedFreeList
• numFreeIntRegs() : UnifiedFreeList
• numFreeLoadEntries() : LSQ< Impl > , LSQUnit< Impl >
• numFreeRegs() : SimpleFreeList
• numFreeStoreEntries() : LSQ< Impl > , LSQUnit< Impl >
• numInFlightFetches() : Minor::Fetch1
• numInService() : Queue< Entry >
• numInsts() : HsaCode
• numIntDestRegs() : BaseDynInst< Impl > , StaticInst
• numIntPhysRegs() : PhysRegFile
• numItems() : X86ISA::MediaOpBase
• numKernels() : BrigObject , HsaObject
• numLoads() : LSQ< Impl > , LSQUnit< Impl >
• numPerfLevels() : DVFSHandler , SrcClockDomain
• numRegs() : ConditionRegisterState , VectorRegisterFile
• numROBFreeEntries() : DefaultCommit< Impl >
• numRunningContexts() : System
• numSimulatedInsts() : BaseCPU
• numSimulatedOps() : BaseCPU
• numSrcRegOperands() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrDirectInst , HsailISA::BrIndirectInst , HsailISA::BrnDirectInst , HsailISA::BrnIndirectInst , HsailISA::Call , HsailISA::CbrDirectInst , HsailISA::CbrIndirectInst , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• numSrcRegs() : BaseDynInst< Impl > , StaticInst
• numStores() : LSQ< Impl > , LSQUnit< Impl >
• numStoresToWB() : LSQ< Impl > , LSQUnit< Impl >
• numSwitches() : Topology
• numUnissuedStores() : Minor::LSQ::StoreBuffer
• numVoltages() : VoltageDomain
• nupc() : GenericISA::DelaySlotUPCState< MachInst > , GenericISA::UPCState< MachInst >
• nxt() : Net::Ip6Hdr , Net::Ip6Opt