- i -
- i2cAddr()
: I2CDevice
- I2CBus()
: I2CBus
- I2CDevice()
: I2CDevice
- i2cStart()
: I2CDevice
- i2digit()
: BaseRemoteGDB
- I386LinuxProcess()
: X86ISA::I386LinuxProcess
- I386Process()
: X86ISA::I386Process
- I8042()
: X86ISA::I8042
- I82094AA()
: X86ISA::I82094AA
- I8237()
: X86ISA::I8237
- I8254()
: X86ISA::I8254
- I8259()
: X86ISA::I8259
- IcachePort()
: FullO3CPU< Impl >::IcachePort
, Minor::Fetch1::IcachePort
, TimingSimpleCPU::IcachePort
, TraceCPU::IcachePort
- icacheRetryRecvd()
: TraceCPU
- id()
: Net::IpHdr
, TimeBuffer< T >
- IdeController()
: IdeController
- IdeDisk()
: IdeDisk
- IdleGen()
: IdleGen
- IdleStartEvent()
: IdleStartEvent
- ie()
: SparcISA::PageTableEntry
- IGbE()
: IGbE
- IGbEInt()
: IGbEInt
- IllegalFrmFault()
: RiscvISA::IllegalFrmFault
- IllegalInstSetStateFault()
: ArmISA::IllegalInstSetStateFault
- ImmOp()
: ImmOp
- in()
: Terminal
- inc()
: Stats::AvgStor
, Stats::StatStor
- incAccessDepth()
: Request
- inCache()
: BaseCache
, BasePrefetcher
, Cache
- incHitCount()
: BaseCache
- incLoadVRFBankConflictCycles()
: GlobalMemPipeline
, LocalMemPipeline
- incMissCount()
: BaseCache
- increaseRefCounter()
: LdsState
- incref()
: RefCounted
- increment()
: AbstractBloomFilter
, BlockBloomFilter
, BulkBloomFilter
, H3BloomFilter
, LSB_CountingBloomFilter
, MultiBitSelBloomFilter
, MultiGrainBloomFilter
, NonCountingBloomFilter
, SatCounter
- increment_credit()
: InputUnit
, OutputUnit
, OutVcState
- increment_flit_network_latency()
: GarnetNetwork
- increment_flit_queueing_latency()
: GarnetNetwork
- increment_hops()
: flit
- increment_injected_flits()
: GarnetNetwork
- increment_injected_packets()
: GarnetNetwork
- increment_packet_network_latency()
: GarnetNetwork
- increment_packet_queueing_latency()
: GarnetNetwork
- increment_received_flits()
: GarnetNetwork
- increment_received_packets()
: GarnetNetwork
- increment_total_hops()
: GarnetNetwork
- incrementCheckCompletions()
: RubyTester
- incrementCycleCompletions()
: RubyDirectedTester
- incrementStats()
: NetworkInterface
- incrFullStat()
: DefaultRename< Impl >
- incrLdIdx()
: LSQUnit< Impl >
- incrStIdx()
: LSQUnit< Impl >
- incrTos()
: ReturnAddrStack
- incWorkItemsBegin()
: System
- incWorkItemsEnd()
: System
- index()
: AlphaISA::TLB
, MipsISA::TLB
, PowerISA::TLB
, RiscvISA::TLB
, VirtDescriptor
- IndirectPredictor()
: IndirectPredictor
- inDrain()
: CopyEngine::CopyEngineChannel
- inExpectedData()
: MemChecker::ByteTracker
- info()
: Stats::DataWrap< Derived, InfoProxyType >
- Info()
: Stats::Info
- info()
: Stats::InfoAccess
- InfoProxy()
: Stats::InfoProxy< Stat, Base >
- IniFile()
: IniFile
- init()
: AbstractController
, AbstractMemory
, AddrMapper
, ArmISA::TableWalker
, ArmISA::TLB
, AtomicSimpleCPU
, BaseCache
, BaseKvmCPU
, BaseRegOperand
, BaseSimpleCPU
, BaseXBar
, BasicLink
, BasicRouter
, Bridge
, CacheMemory
, CheckerCPU
, CoherentXBar
, CommMonitor
, ComputeUnit
, ConditionRegisterState
, CRegOperand
, CrossbarSwitch
, DirectoryMemory
, DistEtherLink
, DistIface
, DistIface::RecvScheduler
, DistIface::Sync
, DmaDevice
, DMASequencer
, DRAMCtrl
, DRAMSim2
, DRegOperand
, EmbeddedPyBind
, EnergyCtrl
, EtherDump
, ExecStage
, ExternalMaster
, ExternalSlave
, FetchStage
, FetchUnit
, FullO3CPU< Impl >
, FunctionRefOperand
, GarnetExtLink
, GarnetIntLink
, GarnetNetwork
, GarnetSyntheticTraffic
, GlobalMemPipeline
, HsailCode
, IGbE
, ImmOperand< T >
, LabelOperand
, ListOperand
, LocalMemPipeline
, LSQUnit< Impl >
, LTAGE::FoldedHistory
, MemCheckerMonitor
, MemDepUnit< MemDepPred, Impl >
, Minor::MinorDynInst
, MinorCPU
, Network
, NetworkInterface
, NoMaliGpu
, NoRegAddrOperand
, Pc
, PerfectSwitch
, PioDevice
, Random
, RegAddrOperand< RegOperandType >
, RegOrImmOperand< RegOperand, T >
, ReturnAddrStack
, Router
, RubyDirectedTester
, RubyPort
, RubyPortProxy
, RubyTester
, ScheduleStage
, ScoreboardCheckStage
, SerialLink
, Shader
, SimObject
, SimpleMemory
, SimpleNetwork
, SimpleRenameMap
, SimPoint
, SRegOperand
, Stats::DistPrint
, Stats::Distribution
, Stats::Histogram
, Stats::SparseHistogram
, Stats::SparseHistPrint
, Stats::Vector2dBase< Derived, Stor >
, Stats::VectorAverageDeviation
, Stats::VectorBase< Derived, Stor >
, Stats::VectorDistribution
, Stats::VectorStandardDeviation
, StatTest
, StoreSet
, Switch
, SwitchAllocator
, System
, Throttle
, TimingSimpleCPU
, TraceCPU::ElasticDataGen
, TraceCPU::FixedRetryGen
, TraceCPU
, TraceGen::InputStream
, TrafficGen
, Tsunami
, UnifiedRenameMap
, VecRegisterState
, WaitClass
, Wavefront
, WireBuffer
, X86ISA::I82094AA
, X86ISA::IntDevice
, X86ISA::Interrupts
- init_addr()
: HsailISA::MemInst
- init_from_vect()
: BaseRegOperand
, CRegOperand
, DRegOperand
, ImmOperand< T >
, RegOrImmOperand< RegOperand, T >
, SRegOperand
- init_net_ptr()
: NetworkInterface
, Router
, Switch
- initAll()
: EmbeddedPyBind
, EmbeddedPython
- initCallArgMem()
: Wavefront
- initFreeList()
: PhysRegFile
- initialized()
: Event
- initializeFlash()
: FlashDevice
- initializeMemory()
: AbstractNVM
, FlashDevice
- initializeStream()
: Prefetcher
- initialTemperature()
: ThermalDomain
- initiate()
: Check
, DirectedGenerator
, InvalidateGenerator
, SeriesRequestGenerator
- initiateAcc()
: BaseO3DynInst< Impl >
, GPUDynInst
, GPUStaticInst
, HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >
, HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
, HsailISA::MemFence
, HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >
, StaticInst
- initiateAction()
: Check
- initiateCheck()
: Check
- initiateFetch()
: ComputeUnit
, FetchUnit
- initiateFlush()
: Check
- initiateMemRead()
: AtomicSimpleCPU
, BaseDynInst< Impl >
, BaseSimpleCPU
, ExecContext
, Minor::ExecContext
, SimpleExecContext
, TimingSimpleCPU
- initiatePrefetch()
: Check
- initiateTranslation()
: BaseDynInst< Impl >
- InitInterrupt()
: X86ISA::InitInterrupt
- initMemProxies()
: CheckerThreadContext< TC >
, O3ThreadContext< class >
, ProxyThreadContext< TC >
, ThreadContext
, ThreadState
- initNetQueues()
: AbstractController
- initNetworkPtr()
: AbstractController
- InitrdSize()
: LinuxAlphaSystem
, LinuxMipsSystem
- InitrdStart()
: LinuxAlphaSystem
, LinuxMipsSystem
- initSectorTable()
: CowDiskImage
- InitStack()
: LinuxAlphaSystem
, LinuxMipsSystem
- initState()
: AlphaProcess
, AlphaSystem
, ArmFreebsdProcess32
, ArmFreebsdProcess64
, ArmLinuxProcess32
, ArmLinuxProcess64
, ArmProcess32
, ArmProcess64
, ArmSystem
, CxxConfigManager
, FreebsdArmSystem
, FuncPageTable
, GenericArmSystem
, LinuxAlphaSystem
, LinuxArmSystem
, LinuxX86System
, MipsProcess
, MultiLevelPageTable< ISAOps >
, PageTableBase
, PowerLinuxProcess
, PowerProcess
, Process
, RiscvProcess
, Root
, SimObject
, Sparc32Process
, Sparc64Process
, SparcProcess
, SparcSystem
, System
, TrafficGen
, X86ISA::I386Process
, X86ISA::Walker::WalkerState
, X86ISA::X86_64Process
, X86System
- initStatistics()
: ExecStage
, ScoreboardCheckStage
- initSummary()
: StoreTrace
- initTrafficType()
: GarnetSyntheticTraffic
- initTransport()
: DistIface
, TCPIface
- initVars()
: BaseDynInst< Impl >
, BaseO3DynInst< Impl >
- initWithStrOffset()
: BaseRegOperand
, CRegOperand
, DRegOperand
, SRegOperand
- injectGlobalMemFence()
: ComputeUnit
- inMissQueue()
: BaseCache
, BasePrefetcher
, Cache
- inPrefetch()
: QueuedPrefetcher
- input()
: Minor::Latch< Data >
- Input()
: Minor::Latch< Data >::Input
- InputBuffer()
: Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits >
- InputEvent()
: BaseRemoteGDB::InputEvent
, GDBListener::InputEvent
- InputStream()
: TraceCPU::ElasticDataGen::InputStream
, TraceCPU::FixedRetryGen::InputStream
, TraceGen::InputStream
- InputUnit()
: InputUnit
- inPwrIdleState()
: DRAMCtrl::Rank
- inRange()
: BaseCache
- inScalarBank()
: ArmISA::VfpMacroOp
- insert()
: AddrRangeMap< V >
, AlphaISA::TLB
, ArmISA::TLB
, DependencyGraph< DynInstPtr >
, EventQueue
, flitBuffer
, InstructionQueue< Impl >
, LSQUnit< Impl >
, MemDepUnit< MemDepPred, Impl >
, Minor::LSQ::StoreBuffer
, MipsISA::TLB
, PowerISA::TLB
, QueuedPrefetcher
, RiscvISA::TLB
, SparcISA::TLB
, SparcISA::TlbMap
, SymbolTable
, Trie< Key, Value >
, X86ISA::GpuTLB
, X86ISA::TLB
- insert_flit()
: OutputUnit
- insertAddr()
: MemFootprintProbe
- insertAt()
: MipsISA::TLB
, PowerISA::TLB
, RiscvISA::TLB
- insertBarrier()
: InstructionQueue< Impl >
, MemDepUnit< MemDepPred, Impl >
- insertBefore()
: Event
- insertBlock()
: BaseSetAssoc
, BaseTags
, FALRU
, LRU
, RandomRepl
- insertCRField()
: PowerISA::PowerStaticInst
- insertFlit()
: VirtualChannel
- insertHardBreak()
: AlphaISA::RemoteGDB
, BaseRemoteGDB
- insertInst()
: ROB< Impl >
- insertKernel()
: GPUCoalescer
- insertLoad()
: LSQ< Impl >
, LSQUnit< Impl >
, StoreSet
- insertNonSpec()
: InstructionQueue< Impl >
, MemDepUnit< MemDepPred, Impl >
- insertRequest()
: GPUCoalescer
, Sequencer
- insertScheduledWakeupTime()
: Consumer
- insertSoftBreak()
: BaseRemoteGDB
- insertStore()
: LSQ< Impl >
, LSQUnit< Impl >
, StoreSet
- insertTableEntry()
: ArmISA::TableWalker
- insertThread()
: FullO3CPU< Impl >
- instAddr()
: BaseDynInst< Impl >
, CheckerCPU
, CheckerThreadContext< TC >
, DefaultCommit< Impl >
, FullO3CPU< Impl >
, GenericISA::PCStateBase
, GPUStaticInst
, O3ThreadContext< class >
, ProxyThreadContext< TC >
, SimpleThread
, ThreadContext
- installGlobals()
: SparcISA::ISA
- installWindow()
: SparcISA::ISA
- instance()
: DrainManager
- instantiate()
: CxxConfigManager
- InstBytes()
: X86ISA::Decoder::InstBytes
- instDone()
: FullO3CPU< Impl >
- InstExecInfo()
: ElasticTrace::InstExecInfo
- InstId()
: Minor::InstId
- instIsHeadInst()
: Minor::Execute
- instIsRightStream()
: Minor::Execute
- instNum()
: GPUStaticInst
- InstPBTrace()
: Trace::InstPBTrace
- InstPBTraceRecord()
: Trace::InstPBTraceRecord
- instReady()
: AlphaISA::Decoder
, ArmISA::Decoder
, MipsISA::Decoder
, PowerISA::Decoder
, RiscvISA::Decoder
, SparcISA::Decoder
, X86ISA::Decoder
- InstRecord()
: Trace::InstRecord
- InstRegIndex()
: X86ISA::InstRegIndex
- instructionBufferHasBranch()
: Wavefront
- InstructionQueue()
: InstructionQueue< Impl >
- insts()
: HsaCode
- instSize()
: GPUStaticInst
, HsailISA::HsailGPUStaticInst
, KernelLaunchStaticInst
- instToCommit()
: DefaultIEW< Impl >
- InstTracer()
: Trace::InstTracer
- IntAssignment()
: X86ISA::IntelMP::IntAssignment
- intClear()
: HDLcd
- intClock()
: IGbE
- IntDevice()
: X86ISA::IntDevice
- Intel8254Timer()
: Intel8254Timer
- IntelTrace()
: Trace::IntelTrace
- IntelTraceRecord()
: Trace::IntelTraceRecord
- Interface()
: EtherLink::Interface
, EtherSwitch::Interface
, Sinic::Interface
- interleaved()
: AddrRange
- IntermediateHeader()
: X86ISA::SMBios::SMBiosTable::SMBiosHeader::IntermediateHeader
- internalMergeFrom()
: SubBlock
- internalMergeTo()
: SubBlock
- Interrupt()
: ArchTimer::Interrupt
- interrupt()
: RiscvISA::RiscvFault
- InterruptLevel()
: SparcISA::Interrupts
- InterruptLevelN()
: SparcISA::InterruptLevelN
- interruptLine()
: PciDevice
- Interrupts()
: AlphaISA::Interrupts
, ArmISA::Interrupts
, MipsISA::Interrupts
, PowerISA::Interrupts
, RiscvISA::Interrupts
, SparcISA::Interrupts
, X86ISA::Interrupts
- interruptsPending()
: MipsISA::Interrupts
- intersect()
: AddrRangeMap< V >
, SparcISA::TlbMap
- intersectionIsEmpty()
: NetDest
, Set
- intersectionIsNotEmpty()
: NetDest
- intersects()
: AddrRange
, CacheBlk::Lock
- IntImmOp()
: PowerISA::IntImmOp
- IntLine()
: X86ISA::IntLine
- intMask()
: HDLcd
- IntMasterPort()
: X86ISA::IntDevice::IntMasterPort
- intNumToBit()
: Pl390
- intNumToWord()
: Pl390
- IntOp()
: PowerISA::IntOp
- intRaise()
: HDLcd
- intrClear()
: IdeDisk
, PciDevice
- IntrControl()
: IntrControl
- IntRegInfo()
: ArmV8KvmCPU::IntRegInfo
- IntrEvent()
: Uart8250::IntrEvent
- IntRotateOp()
: PowerISA::IntRotateOp
- intrPost()
: IdeController
, IdeDisk
, PciDevice
- IntShiftOp()
: PowerISA::IntShiftOp
- IntSinkPin()
: X86ISA::IntSinkPin
- IntSlavePort()
: X86ISA::IntDevice::IntSlavePort
- IntSourcePin()
: X86ISA::IntSourcePin
- intState()
: NoMaliGpu
- intStatus()
: HDLcd
, Uart8250
, Uart
- invalid()
: ArmISA::TableWalker::L2Descriptor
- invalidate()
: BaseSetAssoc
, BaseTags
, CacheBlk
, FALRU
, LRU
, RandomRepl
- invalidateAll()
: X86ISA::GpuTLB
- invalidateBlock()
: Cache
- InvalidateGenerator()
: InvalidateGenerator
- invalidateMiscReg()
: ArmISA::TLB
- invalidateNonGlobal()
: X86ISA::GpuTLB
- invalidateSC()
: Sequencer
- invalidateVisitor()
: Cache
- InvalidOpcode()
: X86ISA::InvalidOpcode
- InvalidTSS()
: X86ISA::InvalidTSS
- invCallback()
: VIPERCoalescer
- invL1()
: VIPERCoalescer
- invoke()
: AlphaISA::AlphaFault
, AlphaISA::ArithmeticFault
, AlphaISA::DtbFault
, AlphaISA::ItbFault
, AlphaISA::ItbPageFault
, AlphaISA::NDtbMissFault
, ArmISA::AbortFault< T >
, ArmISA::ArmFault
, ArmISA::ArmSev
, ArmISA::FlushPipe
, ArmISA::PCAlignmentFault
, ArmISA::Reset
, ArmISA::SecureMonitorCall
, ArmISA::SupervisorCall
, ArmISA::SystemError
, ArmISA::UndefinedInstruction
, ArmISA::VirtualDataAbort
, FaultBase
, GenericAlignmentFault
, GenericISA::M5DebugFault
, GenericPageTableFault
, MipsISA::AddressFault< T >
, MipsISA::CoprocessorUnusableFault
, MipsISA::MipsFaultBase
, MipsISA::NonMaskableInterrupt
, MipsISA::ResetFault
, MipsISA::SoftResetFault
, MipsISA::TlbFault< T >
, ReExec
, RiscvISA::RiscvFault
, SparcISA::FastDataAccessMMUMiss
, SparcISA::FastInstructionAccessMMUMiss
, SparcISA::FillNNormal
, SparcISA::PowerOnReset
, SparcISA::SparcFaultBase
, SparcISA::SpillNNormal
, SparcISA::TrapInstruction
, SyscallRetryFault
, UnimpFault
, X86ISA::InitInterrupt
, X86ISA::InvalidOpcode
, X86ISA::PageFault
, X86ISA::StartupInterrupt
, X86ISA::UnimpInstFault
, X86ISA::X86Abort
, X86ISA::X86FaultBase
, X86ISA::X86Trap
- invoke64()
: ArmISA::ArmFault
- invoke_se()
: RiscvISA::BreakpointFault
, RiscvISA::IllegalFrmFault
, RiscvISA::RiscvFault
, RiscvISA::SyscallFault
, RiscvISA::UnimplementedFault
, RiscvISA::UnknownInstFault
- invwbL1()
: VIPERCoalescer
- IOAPIC()
: X86ISA::IntelMP::IOAPIC
- Iob()
: Iob
- ioctl()
: BaseKvmCPU
, ClDriver
, EmulatedDriver
, Kvm
, KvmDevice
, KvmVM
, PerfKvmCounter
- ioctlRun()
: BaseKvmCPU
- IOIntAssignment()
: X86ISA::IntelMP::IOIntAssignment
- ip()
: Net::IpAddress
- Ip6Ptr()
: Net::Ip6Ptr
- IpAddress()
: Net::IpAddress
- ipdInstNum()
: GPUStaticInst
- IpNetmask()
: Net::IpNetmask
- IpPtr()
: Net::IpPtr
- IPredEntry()
: IndirectPredictor::IPredEntry
- IprEvent()
: TimingSimpleCPU::IprEvent
- IpWithPort()
: Net::IpWithPort
- iqCount()
: DefaultFetch< Impl >
- is_free_signal()
: Credit
- is_stage()
: flit
- is_vc_idle()
: OutputUnit
- ISA()
: AlphaISA::ISA
, ArmISA::ISA
, MipsISA::ISA
, PowerISA::ISA
, RiscvISA::ISA
, SparcISA::ISA
, X86ISA::ISA
- isAbsolute()
: OutputDirectory
- isAcquire()
: GPUDynInst
, GPUStaticInst
, Request
- isAcquireRelease()
: GPUDynInst
, GPUStaticInst
- isActive()
: DmaReadFifo
- IsaFake()
: IsaFake
- isAlignmentFault()
: AlphaISA::AlignmentFault
- isALU()
: GPUDynInst
, GPUStaticInst
- isArgLoad()
: GPUDynInst
, GPUStaticInst
- isArgSeg()
: GPUDynInst
, GPUStaticInst
- isArgSegment()
: Request
- isAtCommit()
: BaseDynInst< Impl >
- isAtomic()
: GPUDynInst
, GPUStaticInst
, Request
- isAtomicAdd()
: GPUDynInst
, GPUStaticInst
- isAtomicAnd()
: GPUDynInst
, GPUStaticInst
- isAtomicCAS()
: GPUDynInst
, GPUStaticInst
- isAtomicDec()
: GPUDynInst
, GPUStaticInst
- isAtomicExch()
: GPUDynInst
, GPUStaticInst
- isAtomicInc()
: GPUDynInst
, GPUStaticInst
- isAtomicMax()
: GPUDynInst
, GPUStaticInst
- isAtomicMin()
: GPUDynInst
, GPUStaticInst
- isAtomicMode()
: System
- isAtomicNoRet()
: GPUDynInst
, GPUStaticInst
- isAtomicNoReturn()
: Request
- isAtomicOp()
: Packet
- isAtomicOr()
: GPUDynInst
, GPUStaticInst
- isAtomicRet()
: GPUDynInst
, GPUStaticInst
- isAtomicReturn()
: Request
- isAtomicSub()
: GPUDynInst
, GPUStaticInst
- isAtomicXor()
: GPUDynInst
, GPUStaticInst
- isattached()
: BaseRemoteGDB
- isAutoDelete()
: Event
- isAvailable()
: DRAMCtrl::Rank
, TraceCPU::ElasticDataGen::HardwareResource
- isBAR()
: PciDevice
- isBarrier()
: GPUDynInst
, GPUStaticInst
, Minor::LSQ::BarrierDataRequest
, Minor::LSQ::LSQRequest
- isBenign()
: X86ISA::X86FaultBase
- isBlockCached()
: Packet
- isBlocked()
: AbstractController
, BaseCache::CacheSlavePort
, BaseCache
- isBlockInvalid()
: CacheMemory
- isBlockNotBusy()
: CacheMemory
- isBranch()
: GPUDynInst
, GPUStaticInst
, Minor::BranchData
- isBroadcast()
: NetDest
, Set
- isBSYSet()
: IdeDisk
- isBubble()
: Minor::BranchData
, Minor::BubbleIF
, Minor::BubbleTraitsAdaptor< ElemType >
, Minor::BubbleTraitsPtrAdaptor< PtrType, ElemType >
, Minor::ForwardInstData
, Minor::ForwardLineData
, Minor::MinorDynInst
, Minor::NoBubbleTraits< ElemType >
, Minor::QueuedInst
- isBusy()
: DistEtherLink::LocalIface
, EtherInt
, EtherLink::Interface
- isCachedAbove()
: Cache
- isCall()
: BaseDynInst< Impl >
, StaticInst
- isCC()
: StaticInst
- isCCPhysReg()
: PhysRegFile
- isClass()
: Net::IpOpt
- isCleanEviction()
: Packet
- isClockSet()
: I2CBus
- isCommitted()
: BaseDynInst< Impl >
- isComp()
: ElasticTrace::TraceInfo
, TraceCPU::ElasticDataGen::GraphNode
- isComplete()
: ArmISA::Stage2LookUp
, MemChecker::WriteCluster
, Minor::Fetch1::FetchRequest
, Minor::LSQ::LSQRequest
- isCompleted()
: BaseDynInst< Impl >
- isCondCtrl()
: BaseDynInst< Impl >
, StaticInst
- isCondDelaySlot()
: BaseDynInst< Impl >
, StaticInst
- isCondRegister()
: BaseOperand
, GPUDynInst
, GPUStaticInst
, HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >
, HsailISA::BrInstBase< TargetType >
, HsailISA::BrnInstBase< TargetType >
, HsailISA::Call
, HsailISA::CbrInstBase< TargetType >
, HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands >
, HsailISA::LdaInstBase< DestOperandType, AddrOperandType >
, HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
, HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType >
, HsailISA::SpecialInst1SrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcNoDest
, HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >
, HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType >
, HsailISA::Stub
, HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType >
, HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType >
, KernelLaunchStaticInst
, RegAddrOperand< RegOperandType >
, RegOrImmOperand< RegOperand, T >
- isCondSwap()
: Request
- isConfReported()
: AbstractMemory
- isConnected()
: BaseMasterPort
, BaseSlavePort
- isControl()
: BaseDynInst< Impl >
, StaticInst
- isCopied()
: Net::IpOpt
- isCPUSequencer()
: RubyPort
- isDataPrefetch()
: BaseDynInst< Impl >
, StaticInst
- isDeadlockEventScheduled()
: DMASequencer
, GPUCoalescer
, RubyPort
, RubyPortProxy
, Sequencer
- isDelayedCommit()
: BaseDynInst< Impl >
, StaticInst
- isDenormalized()
: PowerISA::FloatOp
- isDeviceScope()
: GPUDynInst
, GPUStaticInst
, Request
- isDEVSelect()
: IdeDisk
- isDirectCtrl()
: BaseDynInst< Impl >
, StaticInst
- isDirty()
: BaseCache
, Cache
, CacheBlk
, CacheBlkIsDirtyVisitor
- isDiscardable()
: Minor::Fetch1::FetchRequest
- isDiskSelected()
: IdeController
- isDone()
: ComputeUnit
- isDoneSquashing()
: ROB< Impl >
- isDrained()
: AtomicSimpleCPU
, DefaultCommit< Impl >
, DefaultDecode< Impl >
, DefaultFetch< Impl >
, DefaultIEW< Impl >
, DefaultRename< Impl >
, DrainManager
, FullO3CPU< Impl >
, FUPool
, InstructionQueue< Impl >
, LSQ< Impl >
, MemDepUnit< MemDepPred, Impl >
, Minor::Decode
, Minor::Execute
, Minor::Fetch1
, Minor::Fetch2
, Minor::LSQ
, Minor::LSQ::StoreBuffer
, Minor::Pipeline
, TimingSimpleCPU
- isDraining()
: FullO3CPU< Impl >
- isDstOperand()
: GPUDynInst
, GPUStaticInst
, HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >
, HsailISA::BrInstBase< TargetType >
, HsailISA::BrnInstBase< TargetType >
, HsailISA::Call
, HsailISA::CbrInstBase< TargetType >
, HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands >
, HsailISA::LdaInstBase< DestOperandType, AddrOperandType >
, HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
, HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType >
, HsailISA::SpecialInst1SrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcNoDest
, HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >
, HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType >
, HsailISA::Stub
, HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType >
, HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType >
, KernelLaunchStaticInst
- isElement()
: NetDest
, Set
- isEmpty()
: flitBuffer
, LSQ< Impl >
, LSQUnit< Impl >
, MessageBuffer
, NetDest
, Queue< Entry >
, ROB< Impl >
, Set
, WriteMask
- isEnabled()
: DVFSHandler
- isEnd()
: I2CBus
- isEntry()
: AlphaISA::StackTrace
, ArmISA::StackTrace
, BasicBlock
, MipsISA::StackTrace
, PowerISA::StackTrace
, RiscvISA::StackTrace
, X86ISA::StackTrace
- isEqual()
: NetDest
, Set
- isError()
: MemCmd
, Packet
- isEviction()
: MemCmd
, Packet
- isExecComplete()
: TraceCPU::ElasticDataGen
- isExecuted()
: BaseDynInst< Impl >
- isExit()
: BasicBlock
- isExitEvent()
: Event
- isExpressSnoop()
: Packet
- isFault()
: Minor::ForwardLineData
, Minor::MinorDynInst
- isFaultModelEnabled()
: GarnetNetwork
- isFile()
: OutputDirectory
- isFiltered()
: ArmISA::PMU
- isFirstMicroop()
: BaseDynInst< Impl >
, StaticInst
- isFlagSet()
: Event
- isFlat()
: GPUDynInst
, GPUStaticInst
- isFloating()
: BaseDynInst< Impl >
, StaticInst
- isFloatPhysReg()
: PhysRegFile
- isFlush()
: MemCmd
, Packet
- isFull()
: flitBuffer
, InstructionQueue< Impl >
, LSQ< Impl >
, LSQUnit< Impl >
, Queue< Entry >
, ROB< Impl >
, WriteMask
- isGlbMem()
: ComputeUnit
- isGloballyCoherent()
: GPUDynInst
, GPUStaticInst
- isGlobalMem()
: GPUDynInst
, GPUStaticInst
- isGlobalSeg()
: GPUDynInst
, GPUStaticInst
- isGlobalSegment()
: Request
- isGmInstruction()
: Wavefront
- isGMLdRespFIFOWrRdy()
: GlobalMemPipeline
- isGMReqFIFOWrRdy()
: GlobalMemPipeline
- isGMStRespFIFOWrRdy()
: GlobalMemPipeline
- isGroupSeg()
: GPUDynInst
, GPUStaticInst
- isGroupSegment()
: Request
- isHeadReady()
: ROB< Impl >
- isHWPrefetch()
: MemCmd
- isHyperPriv()
: SparcISA::ISA
- isIENSet()
: IdeDisk
- isInAddrMap()
: AbstractMemory
- isInbetweenInsts()
: Minor::Execute
- isIncoming()
: VirtDescriptor
- isIndirectCtrl()
: BaseDynInst< Impl >
, StaticInst
- isInfinity()
: PowerISA::FloatOp
- isInIQ()
: BaseDynInst< Impl >
- isInLSQ()
: BaseDynInst< Impl >
- isInROB()
: BaseDynInst< Impl >
- isInst()
: Minor::MinorDynInst
- isInState()
: OutVcState
- isInstDataCpuPort()
: RubyTester
- isInstFetch()
: Request
- isInstOnlyCpuPort()
: RubyTester
- isInstPrefetch()
: BaseDynInst< Impl >
, StaticInst
- isInteger()
: BaseDynInst< Impl >
, StaticInst
- isInterrupted()
: Minor::Execute
- isIntPhysReg()
: PhysRegFile
- isInvalidate()
: MemCmd
, Packet
- isInvariantReg()
: ArmKvmCPU
- isIprAccess()
: BaseDynInst< Impl >
, StaticInst
- isIssued()
: BaseDynInst< Impl >
- isKernArgSeg()
: GPUDynInst
, GPUStaticInst
- isKernargSegment()
: Request
- isKernel()
: Request
- isKvmMap()
: AbstractMemory
- isLastMicroop()
: BaseDynInst< Impl >
, StaticInst
- isLastOpInInst()
: Minor::MinorDynInst
- islistening()
: ListenSocket
, TCPIface
- isLLSC()
: MemCmd
, Packet
, Request
- isLmInstruction()
: Wavefront
- isLMReqFIFOWrRdy()
: LocalMemPipeline
- isLMRespFIFOWrRdy()
: LocalMemPipeline
- isLoad()
: BaseDynInst< Impl >
, ElasticTrace::TraceInfo
, GPUDynInst
, GPUStaticInst
, StaticInst
, TraceCPU::ElasticDataGen::GraphNode
- isLocalMem()
: GPUDynInst
, GPUStaticInst
- isLocked()
: AbstractCacheEntry
, CacheMemory
, PersistentTable
- isLockedRMW()
: Request
- isMachineCheckFault()
: MipsISA::MachineCheckFault
- isMacroop()
: BaseDynInst< Impl >
, StaticInst
- isManaged()
: Event
- isMemAddr()
: PhysicalMemory
, System
- isMemBarrier()
: BaseDynInst< Impl >
, StaticInst
- isMemFence()
: GPUDynInst
, GPUStaticInst
- isMemRef()
: BaseDynInst< Impl >
, GPUDynInst
, GPUStaticInst
, Minor::MinorDynInst
, StaticInst
- isMicroBranch()
: BaseDynInst< Impl >
, StaticInst
- isMicroop()
: BaseDynInst< Impl >
, StaticInst
- isMmappedIpr()
: Request
- isMMUFault()
: ArmISA::AbortFault< T >
- isNan()
: PowerISA::FloatOp
- isNegative()
: PowerISA::FloatOp
- isNoCostInst()
: Minor::MinorDynInst
- isNonPriv()
: SparcISA::ISA
- isNonSpeculative()
: BaseDynInst< Impl >
, StaticInst
- isNoOrder()
: GPUDynInst
, GPUStaticInst
- isNop()
: BaseDynInst< Impl >
, GPUDynInst
, GPUStaticInst
, StaticInst
- isNormalized()
: PowerISA::FloatOp
- isNoScope()
: GPUDynInst
, GPUStaticInst
- isNull()
: AbstractMemory
- isNumber()
: Net::IpOpt
- isOldestInstALU()
: Wavefront
- isOldestInstBarrier()
: Wavefront
- isOldestInstFlatMem()
: Wavefront
- isOldestInstGMem()
: Wavefront
- isOldestInstLMem()
: Wavefront
- isOldestInstPrivMem()
: Wavefront
- isopt()
: Net::TcpOpt
- isOutgoing()
: VirtDescriptor
- isOverlap()
: WriteMask
- isPendingModified()
: MSHR
- isPhysMemAddress()
: RubyPort::MemSlavePort
- isPipelined()
: FuncUnit
, FUPool
- isPopable()
: Minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits >
- isPrefetch()
: MemCmd
, Request
, StaticInst
, WholeTranslationState
- isPresent()
: DirectoryMemory
, TBETable< ENTRY >
- isPrint()
: MemCmd
, Packet
- isPriv()
: Request
, SparcISA::ISA
- isPrivateSeg()
: GPUDynInst
, GPUStaticInst
- isPrivateSegment()
: Request
- isPseudoOp()
: HsailISA::Call
- isPTWalk()
: Request
- isQnan()
: PowerISA::FloatOp
- isQuiesce()
: BaseDynInst< Impl >
, StaticInst
- isRead()
: MemCmd
, Packet
- isReadable()
: CacheBlk
- isReadConflict()
: VectorRegisterFile
- isReadOnly()
: X86ISA::PageTableOps
- isReadOnlySeg()
: GPUDynInst
, GPUStaticInst
- isReadonlySegment()
: Request
- isReady()
: flitBuffer
, InputUnit
, MessageBuffer
, NetworkLink
, TimerTable
, VirtualChannel
, WireBuffer
- isReadySrcRegIdx()
: BaseDynInst< Impl >
- isReferenced()
: IniFile::Entry
, IniFile::Section
- isRelaxedOrder()
: GPUDynInst
, GPUStaticInst
- isRelease()
: GPUDynInst
, GPUStaticInst
, Request
- isRequest()
: MemCmd
, Packet
- isReset()
: MSHR::TargetList
- isResponse()
: MemCmd
, Packet
- isResultReady()
: BaseDynInst< Impl >
- isRetrying()
: X86ISA::Walker::WalkerState
- isRetryResp()
: LdsState
- isReturn()
: BaseDynInst< Impl >
, GPUDynInst
, GPUStaticInst
, StaticInst
- iss()
: ArmISA::AbortFault< T >
, ArmISA::ArmFault
, ArmISA::ArmFaultVals< T >
, ArmISA::DataAbort
, ArmISA::SecureMonitorCall
, ArmISA::SupervisorCall
, ArmISA::UndefinedInstruction
- isScalar()
: GPUDynInst
, GPUStaticInst
- isScalarRegister()
: BaseOperand
, GPUDynInst
, GPUStaticInst
, HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >
, HsailISA::BrInstBase< TargetType >
, HsailISA::BrnInstBase< TargetType >
, HsailISA::Call
, HsailISA::CbrInstBase< TargetType >
, HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands >
, HsailISA::LdaInstBase< DestOperandType, AddrOperandType >
, HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
, HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType >
, HsailISA::SpecialInst1SrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcNoDest
, HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >
, HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType >
, HsailISA::Stub
, HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType >
, HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType >
, KernelLaunchStaticInst
, RegAddrOperand< RegOperandType >
, RegOrImmOperand< RegOperand, T >
- isScoped()
: Request
- isSecure()
: CacheBlk
, Packet
, Request
- isSerializeAfter()
: BaseDynInst< Impl >
, StaticInst
- isSerializeBefore()
: BaseDynInst< Impl >
, StaticInst
- isSerializeHandled()
: BaseDynInst< Impl >
- isSerializing()
: BaseDynInst< Impl >
, StaticInst
- isSet()
: AbstractBloomFilter
, BlockBloomFilter
, BulkBloomFilter
, Flags< T >
, H3BloomFilter
, LSB_CountingBloomFilter
, MultiBitSelBloomFilter
, MultiGrainBloomFilter
, NonCountingBloomFilter
, TimerTable
- isShrMem()
: ComputeUnit
- isSimdDone()
: ComputeUnit
- isSnan()
: PowerISA::FloatOp
- isSnooping()
: AddrMapper
, AddrMapper::MapperMasterPort
, AtomicSimpleCPU::AtomicCPUDPort
, BaseCache::CacheMasterPort
, CoherentXBar::CoherentXBarMasterPort
, CommMonitor
, CommMonitor::MonitorMasterPort
, FullO3CPU< Impl >::DcachePort
, MasterPort
, MemCheckerMonitor
, MemCheckerMonitor::MonitorMasterPort
, Minor::LSQ::DcachePort
, SlavePort
, TimingSimpleCPU::DcachePort
, TraceCPU::DcachePort
- isSoft()
: X86ISA::SoftwareInterrupt
, X86ISA::X86FaultBase
- isSpecialOp()
: GPUDynInst
, GPUStaticInst
- isSpillSeg()
: GPUDynInst
, GPUStaticInst
- isSpillSegment()
: Request
- isSquashAfter()
: BaseDynInst< Impl >
, StaticInst
- isSquashed()
: BaseDynInst< Impl >
, TimingSimpleCPU
- isSquashedInIQ()
: BaseDynInst< Impl >
- isSquashedInLSQ()
: BaseDynInst< Impl >
- isSquashedInROB()
: BaseDynInst< Impl >
- isSrcOperand()
: GPUDynInst
, GPUStaticInst
, HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >
, HsailISA::BrInstBase< TargetType >
, HsailISA::BrnInstBase< TargetType >
, HsailISA::Call
, HsailISA::CbrInstBase< TargetType >
, HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands >
, HsailISA::LdaInstBase< DestOperandType, AddrOperandType >
, HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
, HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType >
, HsailISA::SpecialInst1SrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcNoDest
, HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >
, HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType >
, HsailISA::Stub
, HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType >
, HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType >
, KernelLaunchStaticInst
- isStage2()
: ArmISA::AbortFault< T >
, ArmISA::ArmFault
- isStalled()
: ComputeUnit::DTLBPort
, ComputeUnit::ITLBPort
, ComputeUnit::LDSPort
, LSQ< Impl >
, LSQUnit< Impl >
- isStallMapEmpty()
: MessageBuffer
- isStart()
: I2CBus
- isStore()
: BaseDynInst< Impl >
, ElasticTrace::TraceInfo
, GPUDynInst
, GPUStaticInst
, StaticInst
, TraceCPU::ElasticDataGen::GraphNode
- isStoreConditional()
: BaseDynInst< Impl >
, StaticInst
- isStreamChange()
: Minor::BranchData
- isStrictlyOrdered()
: Request
, TraceCPU::ElasticDataGen::GraphNode
, WholeTranslationState
- isSubset()
: AddrRange
, NetDest
, Set
- issue()
: MemDepUnit< MemDepPred, Impl >
, Minor::Execute
- issued()
: StoreSet
- issuedMemBarrierInst()
: Minor::LSQ
- IssueEvent()
: GPUCoalescer::IssueEvent
- issueNext()
: DMASequencer
- issueNextPrefetch()
: Prefetcher
- IssueProbeEvent()
: TLBCoalescer::IssueProbeEvent
- issueRequest()
: GlobalMemPipeline
, GPUCoalescer
, Sequencer
- issueTLBLookup()
: X86ISA::GpuTLB
- issueTranslation()
: X86ISA::GpuTLB
- isSuperset()
: NetDest
, Set
- isSwap()
: Request
- isSWPrefetch()
: MemCmd
- isSyscall()
: BaseDynInst< Impl >
, StaticInst
- isSystemCoherent()
: GPUDynInst
, GPUStaticInst
- isSystemScope()
: GPUDynInst
, GPUStaticInst
, Request
- isTagPresent()
: CacheMemory
, PerfectCacheMemory< ENTRY >
- isTempSerializeAfter()
: BaseDynInst< Impl >
- isTempSerializeBefore()
: BaseDynInst< Impl >
- isThreadSync()
: BaseDynInst< Impl >
, StaticInst
- isTiming()
: X86ISA::Walker::WalkerState
- isTimingMode()
: System
- isTraceComplete()
: TraceCPU::FixedRetryGen
- isTranslationDelayed()
: BaseDynInst< Impl >
- isTtyReq()
: AlphaLinux
, FreeBSD
, Linux
, MipsLinux
, PowerLinux
, SparcLinux
- isUncacheable()
: QueueEntry
, Request
, X86ISA::PageTableOps
- isUncondCtrl()
: BaseDynInst< Impl >
, StaticInst
- isUnconditionalJump()
: GPUDynInst
, GPUStaticInst
- isUnmapped()
: FuncPageTable
, MultiLevelPageTable< ISAOps >
, PageTableBase
- isUnverifiable()
: BaseDynInst< Impl >
, StaticInst
- isUpgrade()
: MemCmd
, Packet
- isValid()
: CacheBlk
, GPUStaticInst
, HsailISA::HsailGPUStaticInst
, KernelLaunchStaticInst
, TraceCPU::FixedRetryGen::TraceElement
, TraceGen::TraceElement
- isValidCounter()
: ArmISA::PMU
- isVecAlu()
: ComputeUnit
- isVectorRegister()
: BaseOperand
, GPUDynInst
, GPUStaticInst
, HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >
, HsailISA::BrInstBase< TargetType >
, HsailISA::BrnInstBase< TargetType >
, HsailISA::Call
, HsailISA::CbrInstBase< TargetType >
, HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands >
, HsailISA::LdaInstBase< DestOperandType, AddrOperandType >
, HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
, HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType >
, HsailISA::SpecialInst1SrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcBase< DestOperandType >
, HsailISA::SpecialInstNoSrcNoDest
, HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >
, HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType >
, HsailISA::Stub
, HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType >
, HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType >
, KernelLaunchStaticInst
, RegAddrOperand< RegOperandType >
, RegOrImmOperand< RegOperand, T >
- isVlan()
: Net::EthHdr
- isVNetOrdered()
: GarnetNetwork
, SimpleNetwork
- isWaitcnt()
: GPUDynInst
, GPUStaticInst
- isWavefrontScope()
: GPUDynInst
, GPUStaticInst
, Request
- isWorkgroupScope()
: GPUDynInst
, GPUStaticInst
, Request
- isWorkitemScope()
: GPUDynInst
, GPUStaticInst
- isWritable()
: CacheBlk
- isWrite()
: MemCmd
, Packet
- isWriteback()
: MemCmd
, Packet
- isWriteBarrier()
: BaseDynInst< Impl >
, StaticInst
- isWriteConflict()
: VectorRegisterFile
- isZero()
: PowerISA::FloatOp
- isZeroReg()
: Scoreboard
- ItbAcvFault()
: AlphaISA::ItbAcvFault
- ItbFault()
: AlphaISA::ItbFault
- ItbPageFault()
: AlphaISA::ItbPageFault
- ITickEvent()
: TimingSimpleCPU::IcachePort::ITickEvent
- ITLBPort()
: ComputeUnit::ITLBPort
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