- r -

• radvProcess() : IGbE
• raise() : X86ISA::IntSourcePin
• raiseInterrupt() : ArmISA::PMU
• raiseInterruptPin() : X86ISA::I82094AA , X86ISA::I8259 , X86ISA::IntDevice
• raiseInterrupts() : Pl011
• Random() : Random
• random() : Random
• RandomGen() : RandomGen
• randomPriority() : MinorCPU
• RandomRepl() : RandomRepl
• RangeAddrMapper() : RangeAddrMapper
• Rank() : DRAMCtrl::Rank
• RankDumpCallback() : DRAMCtrl::RankDumpCallback
• rankParam() : DistIface
• RawDiskImage() : RawDiskImage
• RawObject() : RawObject
• rdtrProcess() : IGbE
• rdy() : WaitClass
• read() : A9SCU , AlphaBackdoor , AmbaFake , BadDevice , BaseRemoteGDB , CircleBuf< T > , ConditionRegisterState , CopyEngine::CopyEngineChannel , CopyEngine , CowDiskImage , CpuLocalTimer , CpuLocalTimer::Timer , DiskImage , DumbTOD , EnergyCtrl , Fifo< T > , FullO3CPU< Impl > , GenericPciHost , GenericTimerMem , Gicv2m , GpuDispatcher , HDLcd , I2CBus , I2CDevice , IdeController , IGbE , Intel8254Timer::Counter , Iob , IsaFake , LdsChunk , LSQ< Impl > , LSQUnit< Impl > , MaltaCChip , MaltaIO , MmDisk , MuxingKvmGic , NoMaliGpu , NSGigE , PciVirtIO , PerfKvmCounter , PioDevice , Pl011 , PL031 , Pl050 , Pl111 , Pl390 , PortProxy , ProtoInputStream , RawDiskImage , RealViewCtrl::Device , RealViewCtrl , RealViewOsc , RealViewTemperatureSensor , SatCounter , SimpleDisk , Sinic::Device , Sp804 , Sp804::Timer , Terminal , Trace::NativeTrace , TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream , TsunamiCChip , TsunamiIO , TsunamiPChip , Uart8250 , UFSHostDevice , VecRegisterState , VectorRegisterFile , VGic , VirtDescriptor , VirtIO9PDiod , VirtIO9PProxy , VirtIO9PSocket , VirtIOBlock , VirtQueue::VirtRing< T > , VncServer , X86ISA::Cmos , X86ISA::I8042 , X86ISA::I82094AA , X86ISA::I8237 , X86ISA::I8254 , X86ISA::I8259 , X86ISA::Interrupts , X86ISA::Speaker
• read1() : VncServer
• readAll() : VirtIO9PProxy
• readArchCCReg() : FullO3CPU< Impl >
• readArchFloatReg() : FullO3CPU< Impl >
• readArchFloatRegInt() : FullO3CPU< Impl >
• readArchIntReg() : FullO3CPU< Impl >
• readBit() : AbstractBloomFilter , BlockBloomFilter , BulkBloomFilter , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter
• readBlob() : FSTranslatingPortProxy , PortProxy , SETranslatingPortProxy
• readByte() : SubBlock
• readCallArgMem() : Wavefront
• readCallback() : GPUCoalescer , Sequencer , UFSHostDevice , UFSHostDevice::UFSSCSIDevice
• readCCReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , O3ThreadContext< class > , PhysRegFile , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readCCRegFlat() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readCCRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readCommand() : IdeDisk
• readComplete() : DRAMSim2
• readCompressedTrace() : RubySystem
• readConfig() : IdeController , PciDevice , VirtIO9PBase , VirtIOBlock , VirtIOConsole , VirtIODeviceBase
• readConfigBlob() : VirtIODeviceBase
• readControl() : IdeDisk
• readCopyBytes() : CopyEngine::CopyEngineChannel
• readCopyBytesComplete() : CopyEngine::CopyEngineChannel
• readCounter() : Intel8254Timer , X86ISA::I8254
• readCpu() : BaseGicRegisters , KvmKernelGicV2 , Pl390
• readCtrl() : VGic
• readData() : MC146818
• readDataOut() : X86ISA::I8042
• readDataTimed() : ArmISA::Stage2MMU
• readDataUntimed() : ArmISA::Stage2MMU
• readDevice() : UFSHostDevice
• readDisk() : IdeDisk
• readDistributor() : BaseGicRegisters , KvmKernelGicV2 , Pl390
• readDone() : UFSHostDevice
• readFillStart() : SparcProcess
• readFlash() : UFSHostDevice::UFSSCSIDevice
• readFloatReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , O3ThreadContext< class > , PhysRegFile , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readFloatRegBits() : CheckerThreadContext< TC > , FullO3CPU< Impl > , O3ThreadContext< class > , PhysRegFile , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readFloatRegBitsFlat() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readFloatRegFlat() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readFloatRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readFloatRegOperandBits() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readFramebuffer() : Pl111
• readFreeEntries() : DefaultRename< Impl >
• readFSReg() : SparcISA::ISA
• readFuncExeInst() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• readGarbage() : UFSHostDevice
• readHeader() : VirtQueue::VirtRing< T >
• readHeadInst() : ROB< Impl >
• readId() : AmbaDevice
• readIntReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , O3ThreadContext< class > , PhysRegFile , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readIntRegFlat() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readIntRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readIob() : Iob
• readIpr() : AlphaISA::ISA
• readJBus() : Iob
• readLastActivate() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• readLastSuspend() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• readMem() : AtomicSimpleCPU , BaseSimpleCPU , CheckerCPU , ExecContext
• ReadMem() : Shader
• readMem() : SimpleExecContext , TimingSimpleCPU
• readMemory() : AbstractNVM , FlashDevice
• readMiscReg() : AlphaISA::ISA , ArmISA::BaseISADevice , ArmISA::DummyISADevice , ArmISA::ISA , ArmISA::PMU , BaseO3DynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , ExecContext , FullO3CPU< Impl > , GenericTimer , GenericTimerISA , GPUExecContext , HsailISA::GPUISA , Minor::ExecContext , MipsISA::ISA , O3ThreadContext< class > , PowerISA::ISA , ProxyThreadContext< TC > , RiscvISA::ISA , SimpleExecContext , SimpleThread , SparcISA::ISA , ThreadContext , X86ISA::ISA
• readMiscRegInt() : ArmISA::PMU
• readMiscRegNoEffect() : AlphaISA::ISA , ArmISA::ISA , CheckerCPU , CheckerThreadContext< TC > , FullO3CPU< Impl > , Minor::ExecContext , MipsISA::ISA , O3ThreadContext< class > , PowerISA::ISA , ProxyThreadContext< TC > , RiscvISA::ISA , SimpleThread , SparcISA::ISA , ThreadContext , X86ISA::ISA
• readMiscRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readNextWindow() : TraceCPU::ElasticDataGen
• readPC() : ArmISA::ArmStaticInst
• readPredicate() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , ProxyThreadContext< TC > , SimpleExecContext , SimpleThread
• readPredTaken() : BaseDynInst< Impl >
• readPredTarg() : BaseDynInst< Impl >
• readQueueFull() : DRAMCtrl
• readReg() : HDLcd , NoMaliGpu , X86ISA::I82094AA , X86ISA::Interrupts
• readRegister() : X86ISA::Cmos
• readRegOtherThread() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext , ThreadContext
• readRegRaw() : NoMaliGpu
• readResult() : BaseDynInst< Impl >
• readSpillStart() : SparcProcess
• readsSCC() : GPUDynInst , GPUStaticInst
• readStallSignals() : DefaultDecode< Impl > , DefaultRename< Impl >
• readStCondFailures() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , ExecContext , Minor::ExecContext , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleExecContext , SimpleThread , ThreadContext
• readString() : SETranslatingPortProxy , X86ISA::SMBios::SMBiosStructure
• readsVCC() : GPUDynInst , GPUStaticInst
• readTailInst() : ROB< Impl >
• readVCpu() : VGic
• readWord() : PixelConverter
• ready() : Wavefront
• readyToCkpt() : DistIface
• readyToCommit() : BaseDynInst< Impl >
• readyToExit() : DistIface
• readyToIssue() : BaseDynInst< Impl >
• ReadyWorkgroup() : ComputeUnit
• RealView() : RealView
• RealViewCtrl() : RealViewCtrl
• RealViewOsc() : RealViewOsc
• RealViewTemperatureSensor() : RealViewTemperatureSensor
• reanalyzeAllMessages() : MessageBuffer
• reanalyzeList() : MessageBuffer
• reanalyzeMessages() : MessageBuffer
• receiveDeviceInterrupt() : Iob
• receiveJBusInterrupt() : Iob
• recordCacheContents() : CacheMemory
• recordCacheTrace() : AbstractController
• recordCPReadCallBack() : GPUCoalescer
• recordCPWriteCallBack() : GPUCoalescer
• recordExecTick() : ElasticTrace
• recordIndirect() : IndirectPredictor
• recordMissLatency() : GPUCoalescer , Sequencer
• recordPCChange() : CheckerCPU
• recordProducer() : InstructionQueue< Impl >
• recordRequestType() : CacheMemory , DirectoryMemory , DMASequencer , GPUCoalescer , Sequencer
• recordResult() : BaseDynInst< Impl >
• recordTarget() : IndirectPredictor
• recordToCommTick() : ElasticTrace
• recreateable() : OutputFile< StreamType > , OutputStream
• recv() : BaseRemoteGDB
• recvAtomic() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , Cache::CpuSidePort , Cache , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , GpuDispatcher::TLBPort , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , MessageSlavePort , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , PioPort , RubyPort::MemSlavePort , RubyPort::PioSlavePort , SerialLink::SerialLinkSlavePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvAtomicSnoop() : AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUDPort , Cache::MemSidePort , Cache , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , TrafficGen::TrafficGenPort
• recvCommand() : CopyEngine::CopyEngineChannel
• recvCutText() : VncServer
• recvDone() : EtherInt
• recvFunctional() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , Cache::CpuSidePort , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , GpuDispatcher::TLBPort , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , RubyPort::MemSlavePort , RubyPort::PioSlavePort , SerialLink::SerialLinkSlavePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvFunctionalSnoop() : AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUDPort , Cache::MemSidePort , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , FullO3CPU< Impl >::DcachePort , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , Minor::LSQ::DcachePort , StubSlavePort , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort , TrafficGen::TrafficGenPort
• recvHeader() : DistIface , TCPIface
• recvKeyboardInput() : VncServer
• recvMessage() : MessageSlavePort , X86ISA::IntDevice::IntSlavePort , X86ISA::IntDevice , X86ISA::Interrupts
• recvPacket() : DistEtherLink::LocalIface , DistIface , EtherInt , EtherLink::Interface , EtherSwitch::Interface , EtherTapInt , IGbEInt , NSGigE , NSGigEInt , Sinic::Device , Sinic::Interface , TCPIface , X86ISA::Walker::WalkerState
• recvPointerInput() : VncServer
• recvRangeChange() : AddrMapper::MapperMasterPort , AddrMapper , BaseXBar , CoherentXBar::CoherentXBarMasterPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , GpuDispatcher::TLBPort , HMCController , LdsState::CuSidePort , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , NoncoherentXBar::NoncoherentXBarMasterPort , RubyPort::MemMasterPort , RubyPort::PioMasterPort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvReal() : EtherTapBase , EtherTapStub
• recvReqRetry() : AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUPort , BaseKvmCPU::KVMCpuPort , Bridge::BridgeMasterPort , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CoherentXBar::SnoopRespPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DefaultFetch< Impl > , DmaPort , FullO3CPU< Impl >::DcachePort , FullO3CPU< Impl >::IcachePort , GarnetSyntheticTraffic::CpuPort , GpuDispatcher::TLBPort , LSQ< Impl > , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , Minor::Fetch1::IcachePort , Minor::Fetch1 , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentXBar::NoncoherentXBarMasterPort , NoncoherentXBar , QueuedMasterPort , RubyDirectedTester::CpuPort , RubyTester::CpuPort , SerialLink::SerialLinkMasterPort , System::SystemPort , TimingSimpleCPU::DcachePort , TimingSimpleCPU::IcachePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , TraceCPU::DcachePort , TraceCPU::IcachePort , TrafficGen , TrafficGen::TrafficGenPort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::Walker , X86ISA::Walker::WalkerPort
• recvResponse() : MessageMasterPort , X86ISA::I82094AA , X86ISA::IntDevice::IntMasterPort , X86ISA::IntDevice , X86ISA::Interrupts
• recvRespRetry() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , CommMonitor::MonitorSlavePort , CommMonitor , DRAMSim2::MemoryPort , DRAMSim2 , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , QueuedSlavePort , SerialLink::SerialLinkSlavePort , SimpleMemory::MemoryPort , SimpleMemory , SlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort
• recvRetry() : BaseXBar::Layer< SrcType, DstType > , LdsState::CuSidePort , LSQUnit< Impl > , MemTest
• recvRetrySnoopResp() : CommMonitor::MonitorMasterPort , CommMonitor , MasterPort , QueuedMasterPort
• RecvScheduler() : DistIface::RecvScheduler
• recvSimulated() : EtherTapBase
• recvTCP() : TCPIface
• recvThreadFunc() : DistIface
• recvTimingReq() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , Cache::CpuSidePort , Cache , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , HMCController , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , RubyPort::MemSlavePort , RubyPort::PioSlavePort , SerialLink::SerialLinkSlavePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , X86ISA::GpuTLB::CpuSidePort
• recvTimingResp() : AbstractController::MemoryPort , AbstractController , AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUPort , BaseKvmCPU::KVMCpuPort , Bridge::BridgeMasterPort , Cache::MemSidePort , Cache , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CoherentXBar::SnoopRespPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DmaPort , FullO3CPU< Impl >::DcachePort , FullO3CPU< Impl >::IcachePort , GarnetSyntheticTraffic::CpuPort , GpuDispatcher::TLBPort , LSQ< Impl > , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , MessageMasterPort , Minor::Fetch1::IcachePort , Minor::Fetch1 , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentXBar::NoncoherentXBarMasterPort , NoncoherentXBar , RubyDirectedTester::CpuPort , RubyPort::MemMasterPort , RubyPort::PioMasterPort , RubyPort , RubyTester::CpuPort , SerialLink::SerialLinkMasterPort , System::SystemPort , TimingSimpleCPU::DcachePort , TimingSimpleCPU::IcachePort , TLBCoalescer::MemSidePort , TraceCPU::DcachePort , TraceCPU::IcachePort , TrafficGen::TrafficGenPort , X86ISA::GpuTLB::MemSidePort , X86ISA::Walker , X86ISA::Walker::WalkerPort
• recvTimingSnoopReq() : AddrMapper::MapperMasterPort , AddrMapper , Cache::MemSidePort , Cache , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , FullO3CPU< Impl >::DcachePort , LSQ< Impl > , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , Minor::LSQ::DcachePort , Minor::LSQ , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort , TraceCPU::IcachePort , TrafficGen::TrafficGenPort
• recvTimingSnoopResp() : AddrMapper::MapperSlavePort , AddrMapper , Cache::CpuSidePort , Cache , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , SlavePort , StubSlavePort
• recvTMsg() : VirtIO9PBase , VirtIO9PProxy
• recycle() : MessageBuffer , WireBuffer
• ReExec() : ReExec
• RefCounted() : RefCounted
• RefCountingPtr() : RefCountingPtr< T >
• refLabel() : HsailCode , LabelMap
• refresh() : PerfKvmCounter , VPtr< T >
• Reg() : CopyEngineReg::Reg< T >
• reg() : EtherBus
• Reg() : iGbReg::Regs::Reg< T >
• regBusy() : ConditionRegisterState , VectorRegisterFile
• regData32() : Sinic::Device
• regData64() : Sinic::Device
• regData8() : Sinic::Device
• regDataAvailCallback() : Terminal
• regenerateBlkAddr() : BaseSetAssoc , BaseTags , FALRU
• regEtraceListeners() : ElasticTrace
• RegImmImmOp() : RegImmImmOp
• RegImmOp() : RegImmOp
• RegImmRegOp() : RegImmRegOp
• RegImmRegShiftOp() : RegImmRegShiftOp
• regIndex() : BaseOperand , BaseRegOperand , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• regionSize() : PoolManager , SimplePoolManager
• registerAbstractController() : RubySystem
• registerCU() : Shader
• registerDequeueCallback() : MessageBuffer
• registerDevice() : PciHost , RealViewCtrl
• registerDrainable() : DrainManager
• registerEvent() : ComputeUnit
• registerHandler() : ExternalMaster , ExternalSlave
• registerKickCallback() : VirtIODeviceBase
• registerNetwork() : RubySystem
• registerPowerProducer() : SubSystem
• registerQueue() : VirtIODeviceBase
• registerSrcClockDom() : VoltageDomain
• registerThreadContext() : System
• registerWithClockDomain() : ClockDomain
• RegMiscRegImmOp() : RegMiscRegImmOp
• regNxtBusy() : VectorRegisterFile
• RegOp() : X86ISA::RegOp
• RegOpBase() : X86ISA::RegOpBase
• RegOpImm() : X86ISA::RegOpImm
• RegOrImmOperand() : RegOrImmOperand< RegOperand, T >
• regProbeListeners() : BaseMemProbe , ElasticTrace , SimObject , SimpleTrace , SimPoint
• regProbePoints() : ArmISA::TLB , AtomicSimpleCPU , BPredUnit , CommMonitor , DefaultCommit< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , PowerModel , SimObject
• RegRegImmImmOp() : RegRegImmImmOp
• RegRegImmImmOp64() : RegRegImmImmOp64
• RegRegImmOp() : RegRegImmOp
• RegRegOp() : RegRegOp
• RegRegRegImmOp() : RegRegRegImmOp
• RegRegRegImmOp64() : RegRegRegImmOp64
• RegRegRegOp() : RegRegRegOp
• RegRegRegRegOp() : RegRegRegRegOp
• regSize() : VecRegisterState
• regsReady() : MemDepUnit< MemDepPred, Impl >
• regsReset() : NSGigE
• regStats() : AbstractController , AbstractMemory , AddressProfiler , AlphaISA::Kernel::Statistics , AlphaISA::TLB , ArmISA::TableWalker , ArmISA::TLB , BaseCache , BaseKvmCPU , BaseO3CPU , BasePrefetcher , BaseSimpleCPU , BaseTags , BaseXBar::Layer< SrcType, DstType > , BaseXBar , BPredUnit , Cache , CacheMemory , CheckerThreadContext< TC > , ClockDomain , ClockedObject , CoherentXBar , CommMonitor , ComputeUnit , ConditionRegisterState , CopyEngine , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DRAMCtrl::Rank , DRAMCtrl , ElasticTrace , EtherDevice , ExecStage , FALRU , FetchStage , FlashDevice , FullO3CPU< Impl > , GarnetNetwork , GlobalMemPipeline , GPUCoalescer , HDLcd , IdeDisk , InstructionQueue< Impl > , Kernel::Statistics , LocalMemPipeline , LSQ< Impl > , LSQUnit< Impl > , MathExprPowerModel , MemDepUnit< MemDepPred, Impl > , MemFootprintProbe , MemTest , MessageBuffer , Minor::MinorStats , MinorCPU , MipsISA::TLB , NoncoherentXBar , O3ThreadContext< class > , PowerISA::TLB , PowerModel , PowerModelState , Prefetcher , Process , Profiler , ProxyThreadContext< TC > , QueuedPrefetcher , RiscvISA::TLB , ROB< Impl > , Router , RubySystem , ScheduleStage , ScoreboardCheckStage , Sequencer , SimObject , SimpleNetwork , SimpleThread , Sinic::Device , SnoopFilter , StackDistProbe , Switch , System , ThermalDomain , ThreadContext , Throttle , Ticked , TickedObject , TLBCoalescer , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TraceCPU , TrafficGen , UFSHostDevice , VecRegisterState , VoltageDomain , Wavefront , X86ISA::GpuTLB
• release() : Event , SimpleMemory , TraceCPU::ElasticDataGen::HardwareResource
• releaseImpl() : Event , PyEvent
• releaseLayer() : BaseXBar::Layer< SrcType, DstType >
• releaseSpace() : LdsState
• releaseStoreBuffer() : TraceCPU::ElasticDataGen::HardwareResource
• reloadRegMap() : SparcISA::ISA
• relocatable() : ElfObject , ObjectFile
• relocate() : OutputFile< StreamType > , OutputStream
• remainingSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• remap() : FlashDevice , FuncPageTable , MultiLevelPageTable< ISAOps > , PageTableBase , Wavefront
• remapAddr() : AddrMapper , RangeAddrMapper
• RemoteGDB() : AlphaISA::RemoteGDB , ArmISA::RemoteGDB , MipsISA::RemoteGDB , PowerISA::RemoteGDB , RiscvISA::RemoteGDB , SparcISA::RemoteGDB , X86ISA::RemoteGDB
• remove() : DependencyGraph< DynInstPtr > , EventQueue , NetDest , OutputDirectory , PacketFifo , PCEvent , PCEventQueue , PollQueue , Set , Trie< Key, Value >
• removeDepOnInst() : TraceCPU::ElasticDataGen::GraphNode
• removeEntries() : LSQ< Impl >
• removeFromHistory() : DefaultRename< Impl >
• removeFrontInst() : FullO3CPU< Impl >
• removeHardBreak() : BaseRemoteGDB
• removeInLSQ() : BaseDynInst< Impl >
• removeInstsNotInROB() : FullO3CPU< Impl >
• removeInstsUntil() : FullO3CPU< Impl >
• removeItem() : Event
• removeListener() : ProbeManager , ProbePoint , ProbePointArg< T >
• removeNetDest() : NetDest
• removeRegDep() : TraceCPU::ElasticDataGen::GraphNode
• removeRegDepMapEntry() : ElasticTrace
• removeRequest() : GPUCoalescer
• removeRobDep() : TraceCPU::ElasticDataGen::GraphNode
• removeSet() : Set
• removeSoftBreak() : BaseRemoteGDB
• removeThread() : FullO3CPU< Impl >
• rename() : CxxConfigManager , DefaultRename< Impl > , SimpleRenameMap , UnifiedRenameMap
• renameCC() : UnifiedRenameMap
• renamedDestRegIdx() : BaseDynInst< Impl >
• renameDestReg() : BaseDynInst< Impl >
• renameDestRegs() : DefaultRename< Impl >
• renamedSrcRegIdx() : BaseDynInst< Impl >
• renameFloat() : UnifiedRenameMap
• RenameHistory() : DefaultRename< Impl >::RenameHistory
• renameInsts() : DefaultRename< Impl >
• renameInt() : UnifiedRenameMap
• renameMisc() : UnifiedRenameMap
• renameSrcReg() : BaseDynInst< Impl >
• renameSrcRegs() : DefaultRename< Impl >
• Renaming() : CxxConfigManager::Renaming
• renderFrame() : BasePixelPump
• renderLine() : BasePixelPump
• renderPixels() : BasePixelPump
• reorderQueue() : DRAMCtrl
• replaceHead() : EventQueue
• replaceThreadContext() : BaseRemoteGDB , CpuEvent , System
• replaceUpgrades() : MSHR::TargetList
• replay() : MemDepUnit< MemDepPred, Impl >
• replayMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• replicatePage() : Process
• reportData() : Minor::BranchData , Minor::Fetch1::FetchRequest , Minor::ForwardInstData , Minor::ForwardLineData , Minor::LSQ::LSQRequest , Minor::MinorDynInst , Minor::QueuedInst , Minor::ReportIF , Minor::ReportTraitsAdaptor< ElemType > , Minor::ReportTraitsPtrAdaptor< PtrType >
• reqIPI() : MaltaCChip , TsunamiCChip
• ReqLayer() : BaseXBar::ReqLayer
• ReqPacketQueue() : ReqPacketQueue
• reqQueueFull() : Bridge::BridgeMasterPort , SerialLink::SerialLinkMasterPort
• Request() : Request
• requestCkpt() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• RequestDesc() : RequestDesc
• requestExit() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• requestFbUpdate() : VncServer
• requestHandler() : UFSHostDevice
• requestInterrupt() : X86ISA::I8259 , X86ISA::Interrupts
• RequestQueue() : VirtIOBlock::RequestQueue
• requestSize() : DmaReadFifo::DmaDoneEvent
• requestStopSync() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• reschedule() : BaseGlobalEvent , EventManager , EventQueue , MemDepUnit< MemDepPred, Impl >
• rescheduleMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• reserve() : BankedArray , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , Minor::Reservable , PacketFifo
• reserved() : PacketFifo
• reservedSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• reserveSpace() : LdsState
• reset() : ActivityRecorder , AlphaISA::Decoder , ArmISA::Decoder , DefaultBTB , DependencyGraph< DynInstPtr > , DmaReadFifo::DmaDoneEvent , IdeDisk , IGbE::DescCache< T > , LocalBP , MemChecker , MipsISA::Decoder , NoMaliGpu , PowerISA::Decoder , ProtoInputStream , ReturnAddrStack , RiscvISA::Decoder , SatCounter , Sinic::Device , SparcISA::Decoder , Stats::AvgSampleStor , Stats::AvgStor , Stats::DataWrapVec< Derived, InfoProxyType > , Stats::DistBase< Derived, Stor > , Stats::DistProxy< Stat > , Stats::DistStor , Stats::Formula , Stats::HistStor , Stats::Info , Stats::InfoAccess , Stats::InfoProxy< Stat, Base > , Stats::ProxyInfo , Stats::SampleStor , Stats::ScalarBase< Derived, Stor > , Stats::SparseHistBase< Derived, Stor > , Stats::SparseHistStor , Stats::StatStor , Stats::ValueBase< Derived > , Stats::Vector2dBase< Derived, Stor > , TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream , VirtIODeviceBase , X86ISA::Decoder
• resetAddr64() : ArmSystem
• resetClock() : Clocked
• resetEntries() : DefaultIEW< Impl > , InstructionQueue< Impl > , LSQ< Impl > , ROB< Impl >
• resetEventCounts() : ArmISA::PMU
• resetFlags() : MSHR::TargetList
• resetLastStopped() : Ticked
• resetOffset() : StorageMap , StorageSpace
• resetStage() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultRename< Impl >
• resetState() : InstructionQueue< Impl > , LSQUnit< Impl > , ROB< Impl >
• resetStats() : AbstractController , BaseSimpleCPU , GPUCoalescer , InputUnit , Router , RubySystem , Sequencer , SimObject , Sinic::Device , Switch
• resize() : DependencyGraph< DynInstPtr > , FrameBuffer , Minor::ForwardInstData , NetDest , SubBlock
• resizeEntries() : LSQ< Impl >
• resizeLQ() : LSQUnit< Impl >
• resizeRegFiles() : ComputeUnit , Wavefront
• resizeSQ() : LSQUnit< Impl >
• resolution() : BaseKvmTimer
• resolve() : OutputDirectory
• resolveFile() : TrafficGen
• resolveSimObject() : CxxConfigManager::SimObjectResolver , PybindSimObjectResolver , SimObjectResolver
• RespLayer() : BaseXBar::RespLayer
• responderHadWritable() : Packet
• responseCommand() : MemCmd
• ResponseEvent() : StubSlavePort::ResponseEvent
• RespPacketQueue() : RespPacketQueue
• respQueueFull() : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• restartClock() : IGbE
• restartCounter() : Sp804::Timer
• restartStateMachine() : CopyEngine::CopyEngineChannel
• restartTimerCounter() : CpuLocalTimer::Timer
• restartWatchdogCounter() : CpuLocalTimer::Timer
• restore() : ReturnAddrStack
• restoreFileOffsets() : FDArray
• result() : Stats::AvgStor , Stats::BinaryNode< Op > , Stats::ConstNode< T > , Stats::ConstVectorNode< T > , Stats::Formula , Stats::FormulaInfoProxy< Stat > , Stats::FormulaNode , Stats::FunctorProxy< T > , Stats::MethodProxy< T, V > , Stats::Node , Stats::ScalarBase< Derived, Stor > , Stats::ScalarInfo , Stats::ScalarInfoProxy< Stat > , Stats::ScalarProxy< Stat > , Stats::ScalarProxyNode< Stat > , Stats::ScalarStatNode , Stats::StatStor , Stats::SumNode< Op > , Stats::UnaryNode< Op > , Stats::ValueBase< Derived > , Stats::ValueProxy< T > , Stats::VectorBase< Derived, Stor > , Stats::VectorInfo , Stats::VectorInfoProxy< Stat > , Stats::VectorProxy< Stat > , Stats::VectorStatNode
• resume() : BasePixelPump::PixelEvent , DrainManager
• resumeFill() : DmaReadFifo
• resumeFillFunctional() : DmaReadFifo
• resumeFillTiming() : DmaReadFifo
• resumeRecvTicks() : DistIface::RecvScheduler
• resyncMatch() : PL031
• Ret() : HsailISA::Ret
• retireHead() : ROB< Impl >
• retireResponse() : Minor::LSQ::LSQRequest , Minor::LSQ::SingleDataRequest , Minor::LSQ::SpecialDataRequest , Minor::LSQ::SplitDataRequest
• retransmit() : EtherTapBase
• retry() : PacketQueue , SyscallReturn , X86ISA::Walker::WalkerState
• retryStalledReq() : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• retryWaiting() : BaseXBar::Layer< SrcType, DstType >
• ReturnAddrStack() : ReturnAddrStack
• returnQueuePush() : LdsState
• returnValue() : SyscallReturn
• rev() : AtagRev
• revokeThreadContext() : Process
• RfeOp() : ArmISA::RfeOp
• RiscvFault() : RiscvISA::RiscvFault
• RiscvLinuxProcess() : RiscvLinuxProcess
• RiscvProcess() : RiscvProcess
• RiscvSystem() : RiscvSystem
• ROB() : ROB< Impl >
• root() : Root
• Root() : Root
• rootdev() : AtagCore
• rotate_counter() : HMCController
• rotateValue() : PowerISA::IntRotateOp
• roundRobin() : DefaultCommit< Impl > , DefaultFetch< Impl >
• roundRobinPriority() : MinorCPU
• route_compute() : Router
• Router() : Router
• routeToHyp() : ArmISA::ArmFault , ArmISA::DataAbort , ArmISA::FastInterrupt , ArmISA::Interrupt , ArmISA::PrefetchAbort , ArmISA::SupervisorCall , ArmISA::SystemError , ArmISA::UndefinedInstruction
• routeToMonitor() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , ArmISA::DataAbort , ArmISA::FastInterrupt , ArmISA::Interrupt , ArmISA::PrefetchAbort , ArmISA::SystemError
• RoutingUnit() : RoutingUnit
• rpc() : Wavefront
• RRSchedulingPolicy() : RRSchedulingPolicy
• RSDP() : X86ISA::ACPI::RSDP
• RSDT() : X86ISA::ACPI::RSDT
• RTC() : MaltaIO::RTC , TsunamiIO::RTC
• RTCEvent() : MC146818::RTCEvent
• RTCTickEvent() : MC146818::RTCTickEvent
• rtralt() : Net::IpOpt
• rtType2Addr() : Net::Ip6Opt
• rtType2SegLft() : Net::Ip6Opt
• rtType2Type() : Net::Ip6Opt
• rtTypeExt() : Net::Ip6Hdr
• ruby_eviction_callback() : RubyPort
• ruby_hit_callback() : RubyPort
• RubyDirectedTester() : RubyDirectedTester
• RubyEvent() : RubySystem::RubyEvent
• RubyPort() : RubyPort
• RubyPortProxy() : RubyPortProxy
• RubyRequest() : RubyRequest
• RubyStatsCallback() : RubyStatsCallback
• RubySystem() : RubySystem
• RubyTester() : RubyTester
• run() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch , StatTest
• rw() : ArmISA::TableWalker::LongDescriptor
• rwTable() : ArmISA::TableWalker::LongDescriptor
• RxDescCache() : IGbE::RxDescCache
• rxDmaDone() : Sinic::Device
• rxDmaReadDone() : NSGigE
• rxDmaWriteDone() : NSGigE
• rxDone() : DistEtherLink::RxLink
• rxDump() : NSGigE , Sinic::Device
• rxFilter() : NSGigE , Sinic::Device
• rxKick() : NSGigE , Sinic::Device
• RxLink() : DistEtherLink::RxLink
• rxReset() : NSGigE
• rxStateMachine() : IGbE