cpu.hh

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/*
 * Copyright (c) 2011-2013 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * Copyright (c) 2011 Regents of the University of California
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Kevin Lim
 *          Korey Sewell
 *          Rick Strong
 */

#ifndef __CPU_O3_CPU_HH__
#define __CPU_O3_CPU_HH__

#include <iostream>
#include <list>
#include <queue>
#include <set>
#include <vector>

#include "arch/types.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu_policy.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/thread_state.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/timebuf.hh"
//#include "cpu/o3/thread_context.hh"
#include "params/DerivO3CPU.hh"
#include "sim/process.hh"

template <class>
class Checker;
class ThreadContext;
template <class>
class O3ThreadContext;

class Checkpoint;
class MemObject;
class Process;

struct BaseCPUParams;

class BaseO3CPU : public BaseCPU
{
    //Stuff that's pretty ISA independent will go here.
  public:
    BaseO3CPU(BaseCPUParams *params);

    void regStats();
};

template <class Impl>
class FullO3CPU : public BaseO3CPU
{
  public:
    // Typedefs from the Impl here.
    typedef typename Impl::CPUPol CPUPolicy;
    typedef typename Impl::DynInstPtr DynInstPtr;
    typedef typename Impl::O3CPU O3CPU;

    typedef O3ThreadState<Impl> ImplState;
    typedef O3ThreadState<Impl> Thread;

    typedef typename std::list<DynInstPtr>::iterator ListIt;

    friend class O3ThreadContext<Impl>;

  public:
    enum Status {
        Running,
        Idle,
        Halted,
        Blocked,
        SwitchedOut
    };

    TheISA::TLB * itb;
    TheISA::TLB * dtb;

    Status _status;

  private:

    class IcachePort : public MasterPort
    {
      protected:
        DefaultFetch<Impl> *fetch;

      public:
        IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
            : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
        { }

      protected:

        virtual bool recvTimingResp(PacketPtr pkt);

        virtual void recvReqRetry();
    };

    class DcachePort : public MasterPort
    {
      protected:

        LSQ<Impl> *lsq;
        FullO3CPU<Impl> *cpu;

      public:
        DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
            : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
              cpu(_cpu)
        { }

      protected:

        virtual bool recvTimingResp(PacketPtr pkt);
        virtual void recvTimingSnoopReq(PacketPtr pkt);

        virtual void recvFunctionalSnoop(PacketPtr pkt)
        {
            // @todo: Is there a need for potential invalidation here?
        }

        virtual void recvReqRetry();

        virtual bool isSnooping() const { return true; }
    };

    class TickEvent : public Event
    {
      private:
        FullO3CPU<Impl> *cpu;

      public:
        TickEvent(FullO3CPU<Impl> *c);

        void process();
        const char *description() const;
    };

    TickEvent tickEvent;

    void scheduleTickEvent(Cycles delay)
    {
        if (tickEvent.squashed())
            reschedule(tickEvent, clockEdge(delay));
        else if (!tickEvent.scheduled())
            schedule(tickEvent, clockEdge(delay));
    }

    void unscheduleTickEvent()
    {
        if (tickEvent.scheduled())
            tickEvent.squash();
    }

    bool tryDrain();

    void drainSanityCheck() const;

    bool isDrained() const;

  public:
    FullO3CPU(DerivO3CPUParams *params);
    ~FullO3CPU();

    void regStats() override;

    ProbePointArg<PacketPtr> *ppInstAccessComplete;
    ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;

    void regProbePoints() override;

    void demapPage(Addr vaddr, uint64_t asn)
    {
        this->itb->demapPage(vaddr, asn);
        this->dtb->demapPage(vaddr, asn);
    }

    void demapInstPage(Addr vaddr, uint64_t asn)
    {
        this->itb->demapPage(vaddr, asn);
    }

    void demapDataPage(Addr vaddr, uint64_t asn)
    {
        this->dtb->demapPage(vaddr, asn);
    }

    void tick();

    void init() override;

    void startup() override;

    int numActiveThreads()
    { return activeThreads.size(); }

    void activateThread(ThreadID tid);

    void deactivateThread(ThreadID tid);

    void insertThread(ThreadID tid);

    void removeThread(ThreadID tid);

    Counter totalInsts() const override;

    Counter totalOps() const override;

    void activateContext(ThreadID tid) override;

    void suspendContext(ThreadID tid) override;

    void haltContext(ThreadID tid) override;

    void updateThreadPriority();

    bool isDraining() const { return drainState() == DrainState::Draining; }

    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;

  public:
    void syscall(int64_t callnum, ThreadID tid, Fault *fault);

    DrainState drain() override;

    void drainResume() override;

    void commitDrained(ThreadID tid);

    void switchOut() override;

    void takeOverFrom(BaseCPU *oldCPU) override;

    void verifyMemoryMode() const override;

    InstSeqNum getAndIncrementInstSeq()
    { return globalSeqNum++; }

    void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);

    Fault hwrei(ThreadID tid);

    bool simPalCheck(int palFunc, ThreadID tid);

    Fault getInterrupts();

    void processInterrupts(const Fault &interrupt);

    void halt() { panic("Halt not implemented!\n"); }

    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;

    TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);

    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
            ThreadID tid);

    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
            ThreadID tid);

    uint64_t readIntReg(int reg_idx);

    TheISA::FloatReg readFloatReg(int reg_idx);

    TheISA::FloatRegBits readFloatRegBits(int reg_idx);

    TheISA::CCReg readCCReg(int reg_idx);

    void setIntReg(int reg_idx, uint64_t val);

    void setFloatReg(int reg_idx, TheISA::FloatReg val);

    void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);

    void setCCReg(int reg_idx, TheISA::CCReg val);

    uint64_t readArchIntReg(int reg_idx, ThreadID tid);

    float readArchFloatReg(int reg_idx, ThreadID tid);

    uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);

    TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);

    void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);

    void setArchFloatReg(int reg_idx, float val, ThreadID tid);

    void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);

    void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);

    void pcState(const TheISA::PCState &newPCState, ThreadID tid);

    TheISA::PCState pcState(ThreadID tid);

    Addr instAddr(ThreadID tid);

    MicroPC microPC(ThreadID tid);

    Addr nextInstAddr(ThreadID tid);

    void squashFromTC(ThreadID tid);

    ListIt addInst(DynInstPtr &inst);

    void instDone(ThreadID tid, DynInstPtr &inst);

    void removeFrontInst(DynInstPtr &inst);

    void removeInstsNotInROB(ThreadID tid);

    void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);

    inline void squashInstIt(const ListIt &instIt, ThreadID tid);

    void cleanUpRemovedInsts();

    void dumpInsts();

  public:
#ifndef NDEBUG

    int instcount;
#endif

    std::list<DynInstPtr> instList;

    std::queue<ListIt> removeList;

#ifdef DEBUG

    std::set<InstSeqNum> snList;
#endif

    bool removeInstsThisCycle;

  protected:
    typename CPUPolicy::Fetch fetch;

    typename CPUPolicy::Decode decode;

    typename CPUPolicy::Rename rename;

    typename CPUPolicy::IEW iew;

    typename CPUPolicy::Commit commit;

    PhysRegFile regFile;

    typename CPUPolicy::FreeList freeList;

    typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];

    typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];

    typename CPUPolicy::ROB rob;

    std::list<ThreadID> activeThreads;

    Scoreboard scoreboard;

    std::vector<TheISA::ISA *> isa;

    IcachePort icachePort;

    DcachePort dcachePort;

  public:
    enum StageIdx {
        FetchIdx,
        DecodeIdx,
        RenameIdx,
        IEWIdx,
        CommitIdx,
        NumStages };

    typedef typename CPUPolicy::TimeStruct TimeStruct;

    typedef typename CPUPolicy::FetchStruct FetchStruct;

    typedef typename CPUPolicy::DecodeStruct DecodeStruct;

    typedef typename CPUPolicy::RenameStruct RenameStruct;

    typedef typename CPUPolicy::IEWStruct IEWStruct;

    TimeBuffer<TimeStruct> timeBuffer;

    TimeBuffer<FetchStruct> fetchQueue;

    TimeBuffer<DecodeStruct> decodeQueue;

    TimeBuffer<RenameStruct> renameQueue;

    TimeBuffer<IEWStruct> iewQueue;

  private:
    ActivityRecorder activityRec;

  public:
    void activityThisCycle() { activityRec.activity(); }

    void activateStage(const StageIdx idx)
    { activityRec.activateStage(idx); }

    void deactivateStage(const StageIdx idx)
    { activityRec.deactivateStage(idx); }

    void wakeCPU();

    virtual void wakeup(ThreadID tid) override;

    ThreadID getFreeTid();

  public:
    ThreadContext *
    tcBase(ThreadID tid)
    {
        return thread[tid]->getTC();
    }

    InstSeqNum globalSeqNum;//[Impl::MaxThreads];

    Checker<Impl> *checker;

    System *system;

    std::vector<Thread *> thread;

    std::list<int> cpuWaitList;

    Cycles lastRunningCycle;

    Tick lastActivatedCycle;

    std::map<ThreadID, unsigned> threadMap;

    std::vector<ThreadID> tids;

    Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
               int load_idx)
    {
        return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx);
    }

    Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
                uint8_t *data, int store_idx)
    {
        return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
                                         data, store_idx);
    }

    MasterPort &getInstPort() override { return icachePort; }

    MasterPort &getDataPort() override { return dcachePort; }

    Stats::Scalar timesIdled;
    Stats::Scalar idleCycles;
    Stats::Scalar quiesceCycles;
    Stats::Vector committedInsts;
    Stats::Vector committedOps;
    Stats::Formula cpi;
    Stats::Formula totalCpi;
    Stats::Formula ipc;
    Stats::Formula totalIpc;

    //number of integer register file accesses
    Stats::Scalar intRegfileReads;
    Stats::Scalar intRegfileWrites;
    //number of float register file accesses
    Stats::Scalar fpRegfileReads;
    Stats::Scalar fpRegfileWrites;
    //number of CC register file accesses
    Stats::Scalar ccRegfileReads;
    Stats::Scalar ccRegfileWrites;
    //number of misc
    Stats::Scalar miscRegfileReads;
    Stats::Scalar miscRegfileWrites;
};

#endif // __CPU_O3_CPU_HH__