Here is a list of all class members with links to the classes they belong to:

- o -

• O3Checker() : O3Checker
• O3CPU : BaseO3DynInst< Impl > , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , O3CPUImpl , O3ThreadContext< class > , O3ThreadState< class > , ROB< Impl >
• O3ThreadContext< Impl > : FullO3CPU< Impl >
• O3ThreadState() : O3ThreadState< class >
• obj : ArmISA::PMU::EventType
• object : CpuEventWrapper< T, F > , EventWrapper< T, F > , MakeCallback< T, F > , ProbeListenerArg< T, Arg > , ProbeManager , Stats::MethodProxy< T, V > , Ticked
• objectExists() : CxxConfigFileBase , CxxIniFile
• ObjectFile() : ObjectFile
• ObjectMatch() : ObjectMatch
• objectParamsByName : CxxConfigManager
• objectsByName : CxxConfigManager
• objectsInOrder : CxxConfigManager
• objFile : Process
• objName : DistEtherLink::Link , EtherLink::Link , EtherSwitch::Interface::PortFifo , EventQueue
• objNameResolver : CheckpointIn
• observeAccess() : BasePrefetcher
• observeMiss() : Prefetcher
• observePfHit() : Prefetcher
• observePfMiss() : Prefetcher
• occupancies : BaseTags
• occupanciesTaskId : BaseTags
• occupancy : BaseXBar::Layer< SrcType, DstType > , Minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits >
• occupiedSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• occupy() : TraceCPU::ElasticDataGen::HardwareResource
• occupyLayer() : BaseXBar::Layer< SrcType, DstType >
• oct : cp::Format
• oemap : FDArray
• oemID : X86ISA::ACPI::RSDP , X86ISA::ACPI::SysDescTable , X86ISA::IntelMP::ConfigTable
• oemRevision : X86ISA::ACPI::SysDescTable
• oemTableAddr : X86ISA::IntelMP::ConfigTable
• oemTableID : X86ISA::ACPI::SysDescTable
• oemTableSize : X86ISA::IntelMP::ConfigTable
• oeSet : PowerISA::IntOp
• off() : Net::EthPtr , Net::Ip6Ptr , Net::IpPtr , Net::TcpHdr , Net::TcpPtr , Net::UdpPtr
• OFF_DEVICE_FEATURES : PciVirtIO
• OFF_DEVICE_STATUS : PciVirtIO
• OFF_GUEST_FEATURES : PciVirtIO
• OFF_ISR_STATUS : PciVirtIO
• OFF_QUEUE_ADDRESS : PciVirtIO
• OFF_QUEUE_NOTIFY : PciVirtIO
• OFF_QUEUE_SELECT : PciVirtIO
• OFF_QUEUE_SIZE : PciVirtIO
• off_t : ArmFreebsd32 , ArmFreebsd64 , ArmLinux32 , ArmLinux64 , FreeBSD , Linux , RiscvLinux , Solaris
• OFF_VIO_DEVICE : PciVirtIO
• offlg : Net::ip6_opt_fragment
• offset : AddrOperandBase , AlphaISA::VAddr , ArchTimer , ArmISA::ArmFault::FaultVals , ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , ArmISA::Decoder , ArmISA::MemoryReg64 , Bitmap::FileHeader , Brig::BrigOperandAddress , HDLcd , Intel8254Timer::Counter , MC146818::RTCEvent , MC146818::RTCTickEvent , MipsISA::InterruptFault , MipsISA::MipsFault< T > , MipsISA::MipsFaultBase::FaultVals , MipsISA::MipsFaultBase , MipsISA::TlbRefillFault , OPTR , PixelConverter::Channel , PowerISA::VAddr , Stats::VectorProxy< Stat > , StorageElement , UFSHostDevice::SCSIReply , UFSHostDevice::transferInfo , X86ISA::Decoder
• offset64() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T >
• offsetBits() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor , StoreSet
• OffsetMask : MipsISA::PTE
• offsetMask : PageTableBase
• OffsetMask : PowerISA::PTE , RiscvISA::PTE
• offsets : HsaQueueEntry
• OFSchedPolicy : Scheduler
• OFSchedulingPolicy() : OFSchedulingPolicy
• okToIssueStarving() : PersistentTable
• old_eq : EventQueue::ScopedMigration
• oldBarrierCnt : Wavefront
• oldDgpr : Wavefront
• oldDgprId : Wavefront
• oldDgprTcnt : Wavefront
• oldestInFlightRobNum : TraceCPU::ElasticDataGen::HardwareResource
• oldestInst : InstructionQueue< Impl >::ListOrderEntry
• oldestReady() : DefaultCommit< Impl >
• OldestReady : DefaultCommit< Impl >
• oldR11Val : Trace::X86NativeTrace
• oldRcxVal : Trace::X86NativeTrace
• oldRealR11Val : Trace::X86NativeTrace
• oldRealRcxVal : Trace::X86NativeTrace
• oldState : Trace::ArmNativeTrace::ThreadState
• oldVgpr : Wavefront
• oldVgprId : Wavefront
• oldVgprTcnt : Wavefront
• onCpuTimerInterrupt() : MipsISA::Interrupts
• onData : BasePrefetcher
• OneByteOpcodeState : X86ISA::Decoder
• onEndOfBlock() : DmaReadFifo , HDLcd::DmaEngine
• OneShot : Intel8254Timer
• oneTraceComplete : TraceCPU
• onFrameDone() : BasePixelPump , HDLcd::PixelPump
• onHSyncBegin() : BasePixelPump
• onHSyncEnd() : BasePixelPump
• onIdle() : DmaReadFifo , HDLcd::DmaEngine
• onInst : BasePrefetcher
• onInterrupt() : NoMaliGpu
• onKvmExitHypercall() : ArmKvmCPU
• onMiss : BasePrefetcher
• onNotify() : VirtIOConsole::TermRecvQueue , VirtIODeviceBase , VirtQueue
• onNotifyDescriptor() : VirtIO9PBase::FSQueue , VirtIOBlock::RequestQueue , VirtIOConsole::TermTransQueue , VirtQueue
• onRead : BasePrefetcher
• onReset() : CustomNoMaliGpu , NoMaliGpu
• onRetryList() : RubyPort
• onUnderrun() : BasePixelPump , HDLcd::PixelPump
• onVSyncBegin() : BasePixelPump , HDLcd::PixelPump
• onVSyncEnd() : BasePixelPump , HDLcd::PixelPump
• onWrite : BasePrefetcher
• op : MathExpr::Node , MathExpr::OpSearch , TimingExprBin , TimingExprUn , X86ISA::ExtMachInst
• op1 : ArmISA::BranchImmImmReg64 , ArmISA::BranchImmReg64 , ArmISA::BranchImmReg , ArmISA::BranchReg64 , ArmISA::BranchReg , ArmISA::BranchRegReg , ArmISA::DataImmOp , ArmISA::DataRegOp , ArmISA::DataRegRegOp , ArmISA::DataX1Reg2ImmOp , ArmISA::DataX1RegImmOp , ArmISA::DataX1RegOp , ArmISA::DataX2RegImmOp , ArmISA::DataX2RegOp , ArmISA::DataX3RegOp , ArmISA::DataXCondCompImmOp , ArmISA::DataXCondCompRegOp , ArmISA::DataXCondSelOp , ArmISA::DataXERegOp , ArmISA::DataXImmOp , ArmISA::DataXSRegOp , ArmISA::FpCondCompRegOp , ArmISA::FpCondSelOp , ArmISA::FpRegRegImmOp , ArmISA::FpRegRegOp , ArmISA::FpRegRegRegCondOp , ArmISA::FpRegRegRegImmOp , ArmISA::FpRegRegRegOp , ArmISA::FpRegRegRegRegOp , ArmISA::MicroNeonMixLaneOp64 , ArmISA::MicroNeonMixOp64 , ArmISA::MicroNeonMixOp , ArmISA::Swap , McrrOp , MiscRegRegImmOp , MrrcOp , MsrRegOp , RegImmRegOp , RegImmRegShiftOp , RegMiscRegImmOp , RegRegImmImmOp64 , RegRegImmImmOp , RegRegImmOp , RegRegOp , RegRegRegImmOp64 , RegRegRegImmOp , RegRegRegOp , RegRegRegRegOp
• op2 : ArmISA::BranchRegReg , ArmISA::DataRegOp , ArmISA::DataRegRegOp , ArmISA::DataX2RegImmOp , ArmISA::DataX2RegOp , ArmISA::DataX3RegOp , ArmISA::DataXCondCompRegOp , ArmISA::DataXCondSelOp , ArmISA::DataXERegOp , ArmISA::DataXSRegOp , ArmISA::FpCondCompRegOp , ArmISA::FpCondSelOp , ArmISA::FpRegRegRegCondOp , ArmISA::FpRegRegRegImmOp , ArmISA::FpRegRegRegOp , ArmISA::FpRegRegRegRegOp , McrrOp , RegRegRegImmOp64 , RegRegRegImmOp , RegRegRegOp , RegRegRegRegOp
• op3 : ArmISA::DataX3RegOp , ArmISA::FpRegRegRegRegOp , RegRegRegRegOp
• opClass() : BaseDynInst< Impl > , MinorOpClass , OpDesc , StaticInst
• opClasses : MinorFU , MinorFUTiming , MinorOpClassSet
• opcode : Brig::BrigInstBase , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , X86ISA::ExtMachInst
• opcode_suffix() : HsailISA::ArithInst< DataType, NumSrcOperands > , HsailISA::CmpInst< DestDataType, SrcDataType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::CvtInst< DestDataType, SrcDataType > , HsailISA::PopcountInst< DestDataType, SrcDataType >
• OpDesc() : OpDesc
• opDescList : FUDesc
• open() : ClDriver , CowDiskImage , EmulatedDriver , OutputDirectory , RawDiskImage , Stats::Text
• openboot : SparcSystem
• openbootSymtab : SparcSystem
• openFile() : FDArray
• openFlagTable : AlphaLinux , ArmFreebsd32 , ArmFreebsd64 , ArmLinux32 , ArmLinux64 , MipsLinux , PowerLinux , RiscvLinux , SparcLinux , SparcSolaris , X86Linux32 , X86Linux64
• openInputFile() : FDArray
• openOutputFile() : FDArray
• openRow : DRAMCtrl::Bank
• openSpecialFile() : Linux , OperatingSystem
• operands : Brig::BrigDirectiveControl , Brig::BrigDirectivePragma , Brig::BrigInstBase
• operandsReady() : VectorRegisterFile
• OperandsSectionIndex : BrigObject
• OperandType : HsailISA::HsailDataType< _OperandType, _CType, _memType, _vgprType, IsBits >
• operateMessageBuffer() : PerfectSwitch
• operateVnet() : PerfectSwitch , Throttle
• Operator : MathExpr
• operator Addr() : AlphaISA::VAddr , PowerISA::VAddr
• operator bool() : Debug::SimpleFlag , Net::EthPtr , Net::Ip6Ptr , Net::IpPtr , Net::TcpPtr , Net::UdpPtr , RefCountingPtr< T >
• operator char *() : Arguments
• operator const EthHdr *() : Net::EthPtr
• operator const Type() : BitfieldBackend::BitUnionOperators< Type, Base > , Flags< T >
• operator double() : Time
• operator EthHdr *() : Net::EthPtr
• operator float() : Float16
• operator int64_t() : BitfieldBackend::SignedBitfieldTypes< Type >::SignedBitfield< first, last > , BitfieldBackend::SignedBitfieldTypes< Type >::SignedBitfieldWO< first, last >
• operator NodePtr &() : Stats::Temp
• operator T() : Arguments
• operator T *() : Arguments , TypedBufferArg< T > , VPtr< T >
• operator timespec() : Time
• operator timeval() : Time
• operator uint32_t() : m5_twin32_t
• operator uint64_t() : AlphaISA::PageTableEntry , BitfieldBackend::RegularBitfieldTypes< Type >::Bitfield< first, last > , BitfieldBackend::RegularBitfieldTypes< Type >::BitfieldWO< first, last > , Cycles , m5_twin64_t , Net::EthAddr
• operator!() : Arguments , Debug::SimpleFlag , Net::EthPtr , Net::Ip6Ptr , Net::IpPtr , Net::TcpPtr , Net::UdpPtr , RefCountingPtr< T > , VPtr< T >
• operator!=() : AddrRange , GenericISA::DelaySlotPCState< MachInst > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::PCStateBase , GenericISA::UPCState< MachInst > , MemCmd
• operator()() : AtomicOpFunctor , CacheBlkIsDirtyVisitor , CacheBlkVisitor , CacheBlkVisitorWrapper , CopyEngineReg::Reg< T > , EtherSwitch::Interface::PortFifo::EntryOrder , iGbReg::Regs::Reg< T > , InstructionQueue< Impl >::pqCompare , ltseqnum , m5::stl_helpers::ContainerPrint< T > , PCEventQueue::MapCompare , SNHash , SparcISA::PageTableEntry , Stats::DistPrint , Stats::ScalarPrint , Stats::SparseHistPrint , Stats::VectorPrint , std::hash< ArmISA::ExtMachInst > , std::hash< BasicBlockRange > , std::hash< FutexKey > , std::hash< PowerISA::ExtMachInst > , std::hash< X86ISA::ExtMachInst > , StringWrap , TestClass , TypedAtomicOpFunctor< T >
• operator*() : Net::EthPtr , Net::Ip6Ptr , Net::IpPtr , Net::TcpPtr , Net::UdpPtr , RefCountingPtr< T > , TimeBuffer< T >::wire , TypedBufferArg< T > , VPtr< T >
• operator*=() : LinearEquation
• operator+() : Cycles , LinearEquation , VPtr< T >
• operator++() : Arguments , Cycles , Stats::ScalarBase< Derived, Stor > , Stats::ScalarProxy< Stat > , TimeBuffer< T >::wire
• operator+=() : Arguments , Cycles , Stats::Formula , Stats::ScalarBase< Derived, Stor > , Stats::ScalarProxy< Stat > , Time , TimeBuffer< T >::wire , VPtr< T >
• operator-() : Cycles
• operator--() : Arguments , Cycles , Stats::ScalarBase< Derived, Stor > , Stats::ScalarProxy< Stat > , TimeBuffer< T >::wire
• operator-=() : Arguments , Stats::ScalarBase< Derived, Stor > , Stats::ScalarProxy< Stat > , Time , TimeBuffer< T >::wire
• operator->() : Net::EthPtr , Net::Ip6Ptr , Net::IpPtr , Net::TcpPtr , Net::UdpPtr , RefCountingPtr< T > , TimeBuffer< T >::wire , TypedBufferArg< T > , VPtr< T >
• operator/=() : Stats::Formula
• operator<() : AddrRange , BitfieldBackend::BitUnionOperators< Type, Base > , MemChecker::Transaction , PciBusAddr , QueuedPrefetcher::DeferredPacket , SparcISA::TlbRange
• operator<< : Cycles , Minor::Execute , Minor::Fetch1 , Minor::LSQ
• operator<=() : QueuedPrefetcher::DeferredPacket
• operator=() : AbstractMemory , AddressProfiler , AlphaISA::PageTableEntry , AlphaISA::VAddr , Arguments , BitfieldBackend::BitUnionOperators< Type, Base > , BitfieldBackend::RegularBitfieldTypes< Type >::Bitfield< first, last > , BitfieldBackend::RegularBitfieldTypes< Type >::BitfieldRO< first, last > , BitfieldBackend::SignedBitfieldTypes< Type >::SignedBitfield< first, last > , BitfieldBackend::SignedBitfieldTypes< Type >::SignedBitfieldRO< first, last > , Bitmap::BmpPixel32 , CacheBlk , CacheMemory , CacheRecorder , CheckTable , Clocked , CopyEngineReg::Reg< T > , DataBlock , DirectoryMemory , Flags< T > , GarnetNetwork , GPUCoalescer , iGbReg::Regs::Reg< T > , Kvm , KvmKernelGicV2 , KvmVM , LdsState , m5_twin32_t , m5_twin64_t , MemState , Minor::ForwardInstData , Net::EthAddr , Net::EthPtr , Net::Ip6Ptr , Net::IpPtr , Net::TcpPtr , Net::UdpPtr , NetDest , Network , PciHost::DeviceInterface , PerfectCacheMemory< ENTRY > , PerfectSwitch , PerfKvmCounter , PersistentTable , PhysicalMemory , PowerISA::VAddr , Profiler , ProtoStream , RefCounted , RefCountingPtr< T > , RubyDirectedTester , RubySystem , RubyTester , Sequencer , Serializable::ScopedCheckpointSection , Set , SimpleNetwork , SparcISA::PageTableEntry , SparcISA::TteTag , Stats::DataWrap< Derived, InfoProxyType > , Stats::DataWrapVec< Derived, InfoProxyType > , Stats::DistProxy< Stat > , Stats::Formula , Stats::ScalarBase< Derived, Stor > , Stats::ScalarProxy< Stat > , Stats::VectorProxy< Stat > , Switch , TBETable< ENTRY > , Throttle , Time , TimeBuffer< T >::wire , TimerTable , VirtDescriptor , VPtr< T > , WireBuffer , X86ISA::I386Process::VSyscallPage , X86ISA::X86_64Process::VSyscallPage , X86ISA::X86Process
• operator==() : AddrRange , BitfieldBackend::BitUnionOperators< Type, Base > , BPredUnit::PredictorHistory , CopyEngineReg::Reg< T > , FutexKey , GenericISA::DelaySlotPCState< MachInst > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::PCStateBase , GenericISA::UPCState< MachInst > , iGbReg::Regs::Reg< T > , MemCmd , Minor::InstId , SparcISA::TlbRange
• operator>() : Cycles , QueuedPrefetcher::DeferredPacket
• operator>>() : Cycles
• operator[]() : Arguments , FDArray , H3BloomFilter , LinearEquation , LinearSystem , MultiBitSelBloomFilter , NonCountingBloomFilter , Stats::Vector2dBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor > , Stats::VectorProxy< Stat > , StridePrefetcher::PCTable , TimeBuffer< T > , TypedBufferArg< T >
• opLat : MinorFU , OpDesc
• opLatencies : FuncUnit
• opLatency() : FuncUnit
• ops : MathExpr
• opsCommitted : DefaultCommit< Impl >
• opSize() : BaseOperand , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T > , X86ISA::ExtMachInst , X86ISA::X86MicroopBase
• OpSys : ObjectFile
• opSys : ObjectFile
• options() : Net::IpHdr , Net::TcpHdr
• OR() : NetDest , Set
• order : BaseCache , MSHR::Target , QueueEntry , WriteQueueEntry::Target
• ORHostControllerEnable : UFSHostDevice::HCIMem
• ORHostControllerStatus : UFSHostDevice::HCIMem
• origAddr : AddrMapper::AddrMapperSenderState
• originalRanges : RangeAddrMapper
• origLength : LTAGE::FoldedHistory
• origPC : X86ISA::Decoder
• ORInterruptEnable : UFSHostDevice::HCIMem
• ORInterruptStatus : UFSHostDevice::HCIMem
• orMask() : WriteMask
• ORUECDL : UFSHostDevice::HCIMem
• ORUECDME : UFSHostDevice::HCIMem
• ORUECN : UFSHostDevice::HCIMem
• ORUECPA : UFSHostDevice::HCIMem
• ORUECT : UFSHostDevice::HCIMem
• ORUTRIACR : UFSHostDevice::HCIMem
• os : Packet::PrintReqState
• Osc0 : RealViewCtrl
• Osc1 : RealViewCtrl
• Osc2 : RealViewCtrl
• Osc3 : RealViewCtrl
• Osc4 : RealViewCtrl
• OstreamLogger() : Trace::OstreamLogger
• ot : OPTR
• OtherFault : SparcISA::TLB
• out : m5::stl_helpers::ContainerPrint< T > , Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , Terminal
• outArgCount : Brig::BrigDirectiveExecutable
• outBuffer : X86ISA::PS2Device
• outcome : X86ISA::GpuTLB::TLBEvent
• outCreditLink : NetworkInterface
• outCreditQueue : NetworkInterface
• outerAttrs : ArmISA::TlbEntry
• outerScopeMap : StorageMap
• outerShareable : ArmISA::TlbEntry
• outfile : Terminal
• outFlitQueue : NetworkInterface
• outNetLink : NetworkInterface
• outNode_ptr : NetworkInterface
• outOfBytes : ArmISA::Decoder , X86ISA::Decoder
• outOfOrderDataDelivery : GlobalMemPipeline
• outpoint : LTAGE::FoldedHistory
• outportCompute() : RoutingUnit
• outportComputeCustom() : RoutingUnit
• outportComputeXY() : RoutingUnit
• output() : Minor::Latch< Data >
• Output() : Minor::Latch< Data >::Output
• output : X86ISA::I8259
• output_high : Intel8254Timer::Counter
• outputChar : AlphaAccess , MipsAccess
• OutputDirectory() : OutputDirectory , OutputFile< StreamType > , OutputStream
• outputFifo : EtherSwitch::Interface
• OutputFile() : OutputFile< StreamType >
• outputFull : X86ISA::I8042
• outputHigh() : Intel8254Timer::Counter , Intel8254Timer , X86ISA::I8254
• OutputStream() : OutputStream
• OutputUnit() : OutputUnit
• outputWidth : Minor::Decode , Minor::Fetch2
• outputWire : Minor::Latch< Data >::Output
• outstanding : LSQUnit< Impl >::LSQSenderState , TimingSimpleCPU::SplitMainSenderState , WholeTranslationState
• outstandingAddrs : MemTest
• outstandingCount() : DMASequencer , GPUCoalescer , RubyPort , RubyPortProxy , Sequencer
• outstandingEvents : DRAMCtrl::Rank
• outstandingMisses() : Cache
• outstandingReadReqs : CommMonitor::MonitorStats
• outstandingReads : DRAMSim2 , MemChecker::ByteTracker
• outstandingReadsHist : CommMonitor::MonitorStats
• outstandingReqs : Wavefront , X86ISA::GpuTLB
• outstandingReqsRdGm : Wavefront
• outstandingReqsRdLm : Wavefront
• outstandingReqsWrGm : Wavefront
• outstandingReqsWrLm : Wavefront
• outstandingResponses : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• outstandingSnoop : Cache , CoherentXBar
• outstandingWriteReqs : CommMonitor::MonitorStats
• outstandingWrites : DRAMSim2
• outstandingWritesHist : CommMonitor::MonitorStats
• OutVcState() : OutVcState
• OVA : ArmISA::ArmFault
• OVAddr : ArmISA::AbortFault< T >
• oVAddr : ArmISA::Stage2MMU::Stage2Translation
• overallAccesses : BaseCache
• overallAvgMissLatency : BaseCache
• overallAvgMshrMissLatency : BaseCache
• overallAvgMshrUncacheableLatency : BaseCache
• overallHits : BaseCache
• overallMisses : BaseCache
• overallMissLatency : BaseCache
• overallMissRate : BaseCache
• overallMshrHits : BaseCache
• overallMshrMisses : BaseCache
• overallMshrMissLatency : BaseCache
• overallMshrMissRate : BaseCache
• overallMshrUncacheable : BaseCache
• overallMshrUncacheableLatency : BaseCache
• overflow : Stats::DistData , Stats::DistStor
• overflow64 : ArmISA::PMU::CounterState
• OverflowTrap() : X86ISA::OverflowTrap
• overrideEc : ArmISA::HypervisorTrap , ArmISA::SecureMonitorTrap , ArmISA::SupervisorCall , ArmISA::SupervisorTrap , ArmISA::UndefinedInstruction
• owner : ExternalMaster::Port , ExternalSlave::Port , Minor::LSQ::SplitDataRequest::TranslationEvent , Port , StubSlavePort::ResponseEvent , Ticked::ClockEvent , TraceCPU::DcachePort , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TraceCPU::IcachePort
• ownerLds : LdsState::CuSidePort