Here is a list of all class members with links to the classes they belong to:

- i -

• i : KvmFPReg , SimpleThread
• i2cAddr : I2CBus , I2CDevice
• I2CBus() : I2CBus
• I2CDevice() : I2CDevice
• i2cStart() : I2CDevice
• I2CState : I2CBus
• i2digit() : BaseRemoteGDB
• I386 : ObjectFile
• I386LinuxProcess() : X86ISA::I386LinuxProcess
• I386Process() : X86ISA::I386Process
• I8042() : X86ISA::I8042
• I82094AA() : X86ISA::I82094AA
• I8237() : X86ISA::I8237
• I8254() : X86ISA::I8254
• I8259() : X86ISA::I8259
• I_ALU : Wavefront
• I_FLAT : Wavefront
• I_GLOBAL : Wavefront
• I_PRIVATE : Wavefront
• I_SHARED : Wavefront
• iam : iGbReg::Regs
• iauxBase : ecoff_fdr
• iauxMax : ecoff_symhdr
• ibrd : Pl011
• ic : Iob
• IcacheAccessComplete : DefaultFetch< Impl >
• icacheGen : TraceCPU
• IcacheNeedsRetry : Minor::Fetch1
• icacheNextEvent : TraceCPU
• icachePort : AtomicSimpleCPU , CheckerCPU , FullO3CPU< Impl >
• IcachePort() : FullO3CPU< Impl >::IcachePort
• icachePort : Minor::Fetch1
• IcachePort() : Minor::Fetch1::IcachePort
• icachePort : TimingSimpleCPU
• IcachePort() : TimingSimpleCPU::IcachePort
• icachePort : TraceCPU
• IcachePort() : TraceCPU::IcachePort
• IcacheRetry : BaseSimpleCPU
• icacheRetryRecvd() : TraceCPU
• IcacheRunning : Minor::Fetch1
• icacheStallCycles : DefaultFetch< Impl > , SimpleExecContext
• icacheState : Minor::Fetch1
• IcacheState : Minor::Fetch1
• IcacheWaitResponse : BaseSimpleCPU , DefaultFetch< Impl >
• IcacheWaitRetry : DefaultFetch< Impl >
• IcacheWaitSwitch : BaseSimpleCPU
• iccrpr : Pl390
• icr : iGbReg::Regs
• id : AbstractController::SenderState , ArmISA::PMU::ProbeListener , ArmKvmCPU::KvmCoreMiscRegInfo , ArmKvmCPU::KvmIntRegInfo , BaseXBar::PortCache , BasicBlock , GarnetSyntheticTraffic , iGbReg::RxDesc , MemDepUnit< MemDepPred, Impl > , MemTest , Minor::Fetch1::FetchRequest , Minor::ForwardLineData , Minor::MinorDynInst , Net::IpHdr , Port , SimPoint::BBInfo , Stats::Info , ThermalNode , TimeBuffer< T > , vring_used_elem , X86ISA::I82094AA , X86ISA::IntelMP::IOAPIC
• ID : X86ISA::PS2Keyboard , X86ISA::PS2Mouse
• ID_9P : VirtIO9PBase
• ID_BLOCK : VirtIOBlock
• ID_CONSOLE : VirtIOConsole
• id_count : Stats::Info
• ID_INVALID : VirtIODummyDevice
• idcode : ArmISA::PMU
• ideConfig : IdeController
• IdeController() : IdeController
• IdeDisk() : IdeDisk
• ident : Net::ip6_opt_fragment
• identification : Brig::BrigModuleHeader
• Idle : BaseKvmCPU , BaseSimpleCPU
• IDLE : BaseXBar::Layer< SrcType, DstType >
• Idle : CopyEngine::CopyEngineChannel , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• IDLE : I2CBus
• Idle : Iob , ROB< Impl >
• idle_dur : ExecStage
• idleCycles : FullO3CPU< Impl > , Ticked
• idleDur : ExecStage
• idleFraction : SimpleExecContext
• IdleGen() : IdleGen
• idlePhaseStart : UFSHostDevice
• idleProcess : AlphaISA::Kernel::Statistics
• idleRate : DefaultFetch< Impl >
• IdleStartEvent() : IdleStartEvent
• idleStartEvent : LinuxAlphaSystem
• idleTimes : UFSHostDevice::UFSHostDeviceStats
• idnMax : ecoff_symhdr
• IdReg : RealViewCtrl
• idRegs : CustomNoMaliGpu
• idx : ArmKvmCPU::KvmCoreMiscRegInfo , ArmKvmCPU::KvmIntRegInfo , ArmV8KvmCPU::IntRegInfo , ArmV8KvmCPU::MiscRegInfo , BankedArray::AccessRecord , FUPool::FUIdxQueue , LSQUnit< Impl >::LSQSenderState , vring_avail , vring_used , X86ISA::InstRegIndex
• idxMask : DefaultBTB
• ie() : SparcISA::PageTableEntry
• ier : dp_regs
• IER : Uart8250
• IEW : DefaultCommit< Impl > , DefaultRename< Impl >
• iew : DefaultRename< Impl >::Stalls , FullO3CPU< Impl >
• IEW : InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , SimpleCPUPolicy< Impl >
• iew_ptr : DefaultRename< Impl >
• iewBlock : TimeBufStruct< Impl >
• iewBlockCycles : DefaultIEW< Impl >
• iewDispatchedInsts : DefaultIEW< Impl >
• iewDispLoadInsts : DefaultIEW< Impl >
• iewDispNonSpecInsts : DefaultIEW< Impl >
• iewDispSquashedInsts : DefaultIEW< Impl >
• iewDispStoreInsts : DefaultIEW< Impl >
• iewExecLoadInsts : DefaultIEW< Impl >
• iewExecRate : DefaultIEW< Impl >
• iewExecSquashedInsts : DefaultIEW< Impl >
• iewExecStoreInsts : DefaultIEW< Impl >
• iewExecutedBranches : DefaultIEW< Impl >
• iewExecutedInsts : DefaultIEW< Impl >
• iewExecutedNop : DefaultIEW< Impl >
• iewExecutedRefs : DefaultIEW< Impl >
• iewExecutedSwp : DefaultIEW< Impl >
• iewIdleCycles : DefaultIEW< Impl >
• IEWIdx : FullO3CPU< Impl >
• iewInfo : TimeBufStruct< Impl >
• iewInstsToCommit : DefaultIEW< Impl >
• iewIQFullEvents : DefaultIEW< Impl >
• iewLSQFullEvents : DefaultIEW< Impl >
• iewQueue : DefaultCommit< Impl > , DefaultIEW< Impl > , FullO3CPU< Impl >
• iewSquashCycles : DefaultIEW< Impl >
• iewStage : DefaultCommit< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl >
• IEWStruct : DefaultCommit< Impl > , DefaultIEW< Impl > , FullO3CPU< Impl > , SimpleCPUPolicy< Impl >
• iewToCommitDelay : DefaultCommit< Impl >
• iewToDecodeDelay : DefaultDecode< Impl >
• iewToFetchDelay : DefaultFetch< Impl >
• iewToRenameDelay : DefaultRename< Impl >
• iewUnblock : TimeBufStruct< Impl >
• iewUnblockCycles : DefaultIEW< Impl >
• iextMax : ecoff_symhdr
• ifd : ecoff_extsym
• ifdMax : ecoff_symhdr
• ifetch_pkt : TimingSimpleCPU
• ifetch_req : AtomicSimpleCPU
• ifls : Pl011
• igbe : IGbE::DescCache< T >
• IGbE() : IGbE
• IGbEInt() : IGbEInt
• Ignore : ArmISA::TableWalker::L1Descriptor
• ignore : Trace::Logger
• ihr : dp_regs
• ihs : Pl111
• iline : pdr
• ilineBase : ecoff_fdr
• ilineMax : ecoff_symhdr
• IllegalAsi : SparcISA::TLB
• IllegalFrmFault() : RiscvISA::IllegalFrmFault
• IllegalInstSetStateFault() : ArmISA::IllegalInstSetStateFault
• image : CowDiskCallback , IdeDisk , MmDisk , SimpleDisk , VirtIOBlock
• imageQuery : Brig::BrigInstQueryImage
• imageSegmentMemoryScope : Brig::BrigInstMemFence
• imageType : Brig::BrigInstImage , Brig::BrigInstQueryImage
• imap : FDArray
• imask : ArchTimer
• imb : PAL
• imcrPresent : X86ISA::IntelMP::FloatingPointer
• imm : ArmISA::BranchImm64 , ArmISA::BranchImm , ArmISA::BranchImmReg64 , ArmISA::BranchImmReg , ArmISA::DataImmOp , ArmISA::DataX1RegImmOp , ArmISA::DataX2RegImmOp , ArmISA::DataXCondCompImmOp , ArmISA::DataXImmOnlyOp , ArmISA::DataXImmOp , ArmISA::FpRegImmOp , ArmISA::FpRegRegImmOp , ArmISA::FpRegRegRegImmOp , ArmISA::MemoryImm64 , ArmISA::MemoryImm , ArmISA::MemoryLiteral64 , ArmISA::MicroIntImmOp , ArmISA::MicroIntImmXOp , ArmISA::MicroMemPairOp , ArmISA::MicroNeonMemOp , ArmISA::PredImmOp , ArmISA::SysDC64 , ImmOp , McrrOp , MiscRegRegImmOp , MrrcOp , MsrImmOp , PowerISA::IntImmOp , RegImmOp , RegImmRegOp , RegImmRegShiftOp , RegMiscRegImmOp , RegRegImmOp , RegRegRegImmOp64 , RegRegRegImmOp
• imm1 : ArmISA::BranchImmImmReg64 , ArmISA::DataX1Reg2ImmOp , RegImmImmOp , RegRegImmImmOp64 , RegRegImmImmOp
• imm2 : ArmISA::BranchImmImmReg64 , ArmISA::DataX1Reg2ImmOp , RegImmImmOp , RegRegImmImmOp64 , RegRegImmImmOp
• imm8 : X86ISA::MediaOpImm , X86ISA::RegOpImm
• imm_op : RegOrImmOperand< RegOperand, T >
• immediate : DistHeaderPkt , X86ISA::ExtMachInst
• immediateCollected : X86ISA::Decoder
• immediateSize : X86ISA::Decoder
• ImmediateState : X86ISA::Decoder
• ImmediateTypeOneByte : X86ISA::Decoder
• ImmediateTypeThreeByte0F38 : X86ISA::Decoder
• ImmediateTypeThreeByte0F3A : X86ISA::Decoder
• ImmediateTypeTwoByte : X86ISA::Decoder
• ImmediateTypeVex : X86ISA::Decoder
• ImmOp() : ImmOp
• imp : ArmISA::PMU
• impl_kern_boundary_sync : Shader
• ImplBits : AlphaISA::VAddr , PowerISA::VAddr
• ImplCPU : BaseDynInst< Impl >
• ImplMask : AlphaISA::VAddr , PowerISA::VAddr
• ImplState : BaseDynInst< Impl > , FullO3CPU< Impl >
• importer : EmbeddedPython
• importerModule : EmbeddedPython
• imr : dp_regs , iGbReg::Regs
• IMR : X86ISA::I8259
• imsc : Pl011
• in() : Terminal
• Inactive : DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• inAddrMap : AbstractMemory , BackingStoreEntry
• inArgCount : Brig::BrigDirectiveExecutable
• inc() : Stats::AvgStor , Stats::StatStor
• incAccessDepth() : Request
• inCache() : BaseCache , BasePrefetcher , Cache , FALRUBlk
• incHitCount() : BaseCache
• incLoadVRFBankConflictCycles() : GlobalMemPipeline , LocalMemPipeline
• includeSquashInst : DefaultIEWDefaultCommit< Impl >
• incMissCount() : BaseCache
• incoming_link : Message
• increaseRefCounter() : LdsState
• inCreditLink : NetworkInterface
• incref() : RefCounted
• increment() : AbstractBloomFilter , BlockBloomFilter , BulkBloomFilter , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter , SatCounter
• increment_credit() : InputUnit , OutputUnit , OutVcState
• increment_flit_network_latency() : GarnetNetwork
• increment_flit_queueing_latency() : GarnetNetwork
• increment_hops() : flit
• increment_injected_flits() : GarnetNetwork
• increment_injected_packets() : GarnetNetwork
• increment_packet_network_latency() : GarnetNetwork
• increment_packet_queueing_latency() : GarnetNetwork
• increment_received_flits() : GarnetNetwork
• increment_received_packets() : GarnetNetwork
• increment_total_hops() : GarnetNetwork
• IncrementAfter : ArmISA::RfeOp , ArmISA::SrsOp
• incremental : VncInput::FrameBufferUpdateReq
• IncrementBefore : ArmISA::RfeOp , ArmISA::SrsOp
• incrementCheckCompletions() : RubyTester
• incrementCycleCompletions() : RubyDirectedTester
• incrementStats() : NetworkInterface
• incrFullStat() : DefaultRename< Impl >
• incrLdIdx() : LSQUnit< Impl >
• incrStIdx() : LSQUnit< Impl >
• incrTos() : ReturnAddrStack
• incWorkItemsBegin() : System
• incWorkItemsEnd() : System
• index() : AlphaISA::TLB , ArmISA::ISA::MiscRegInitializerEntry , ArmISA::MemoryReg , ArmISA::VldSingleOp64 , ArmISA::VstSingleOp64 , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::SQCPort , DataTranslation< ExecContextPtr > , DNR , ecoff_sym
• Index : Minor::Scoreboard
• index() : MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , RNDXR , StackDistCalc , Stats::DistProxy< Stat > , Stats::ScalarProxy< Stat > , TimeBuffer< T > , TimeBuffer< T >::wire , TimingExprRef , TimingExprSrcReg , TimingSimpleCPU::SplitFragmentSenderState , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort
• Index : VirtDescriptor
• index() : VirtDescriptor , VirtQueue::VirtRing< T >::Header
• Index : VirtQueue::VirtRing< T >
• index : X86ISA::EmulEnv , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::MemOp
• indexMask : LocalBP , StoreSet
• IndexNodeMap : StackDistCalc
• indirectHits : BPredUnit
• indirectLookups : BPredUnit
• indirectMispredicted : BPredUnit
• indirectMisses : BPredUnit
• IndirectPredictor() : IndirectPredictor
• inDrain() : CopyEngine::CopyEngineChannel
• inExpectedData() : MemChecker::ByteTracker
• infiniteSD : StackDistProbe
• Infinity : StackDistCalc
• inflight : X86ISA::Walker::WalkerState
• inFlightInsts : Minor::Execute::ExecuteThreadInfo
• inflightLoads : GlobalMemPipeline
• inFlightNodes : TraceCPU::ElasticDataGen::HardwareResource
• inflightStores : GlobalMemPipeline
• info : Bitmap::CompleteV1Header
• INFO : Logger
• Info : Stats::DataWrap< Derived, InfoProxyType >
• info() : Stats::DataWrap< Derived, InfoProxyType >
• Info : Stats::DataWrapVec2d< Derived, InfoProxyType > , Stats::DataWrapVec< Derived, InfoProxyType > , Stats::DistBase< Derived, Stor > , Stats::Info
• info() : Stats::InfoAccess
• Info : Stats::SparseHistBase< Derived, Stor > , Stats::Vector2dBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor >
• info : X86ISA::IntelMP::BusHierarchy
• InfoProxy() : Stats::InfoProxy< Stat, Base >
• inFUMemInsts : Minor::Execute::ExecuteThreadInfo
• iniFile : CxxIniFile
• IniFile() : IniFile
• init() : AbstractController , AbstractMemory , AddrMapper , ArmISA::TableWalker , ArmISA::TLB , AtomicSimpleCPU , BaseCache , BaseKvmCPU , BaseRegOperand , BaseSimpleCPU , BaseXBar , BasicLink , BasicRouter , Bridge , Brig::BrigDirectiveVariable , CacheMemory , CheckerCPU , CoherentXBar , CommMonitor , ComputeUnit , ConditionRegisterState , CRegOperand , CrossbarSwitch , DirectoryMemory , DistEtherLink , DistIface , DistIface::RecvScheduler , DistIface::Sync , DmaDevice , DMASequencer , DRAMCtrl , DRAMSim2 , DRegOperand , EmbeddedPyBind , EnergyCtrl , EtherDump , ExecStage , ExternalMaster , ExternalSlave , FetchStage , FetchUnit , FullO3CPU< Impl > , FunctionRefOperand , GarnetExtLink , GarnetIntLink , GarnetNetwork , GarnetSyntheticTraffic , GlobalMemPipeline , HsailCode , IGbE , ImmOperand< T > , LabelOperand , ListOperand , LocalMemPipeline , LSQUnit< Impl > , LTAGE::FoldedHistory , MemCheckerMonitor , MemDepUnit< MemDepPred, Impl > , Minor::MinorDynInst , MinorCPU , Network , NetworkInterface , NoMaliGpu , NoRegAddrOperand , Pc , PerfectSwitch , PioDevice , Random , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T > , ReturnAddrStack , Router , RubyDirectedTester , RubyPort , RubyPortProxy , RubyTester , ScheduleStage , ScoreboardCheckStage , SerialLink , Shader , SimObject , SimpleMemory , SimpleNetwork , SimpleRenameMap , SimPoint , SRegOperand , Stats::DistPrint , Stats::Distribution , Stats::Histogram , Stats::SparseHistogram , Stats::SparseHistPrint , Stats::Vector2dBase< Derived, Stor > , Stats::VectorAverageDeviation , Stats::VectorBase< Derived, Stor > , Stats::VectorDistribution , Stats::VectorStandardDeviation , StatTest , StoreSet , Switch , SwitchAllocator , System , Throttle , TimingSimpleCPU , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TraceCPU , TraceGen::InputStream , TrafficGen , Tsunami , UnifiedRenameMap , VecRegisterState , WaitClass , Wavefront , WireBuffer , X86ISA::I82094AA , X86ISA::IntDevice , X86ISA::Interrupts
• init_addr() : HsailISA::MemInst
• init_from_vect() : BaseRegOperand , CRegOperand , DRegOperand , ImmOperand< T > , RegOrImmOperand< RegOperand, T > , SRegOperand
• init_net_ptr() : NetworkInterface , Router , Switch
• init_param : System
• initAll() : EmbeddedPyBind , EmbeddedPython
• initCallArgMem() : Wavefront
• initControlWord : X86ISA::I8259
• initFreeList() : PhysRegFile
• initFunc : EmbeddedPyBind
• initial_count : Intel8254Timer::Counter
• initialApicId : X86ISA::I82094AA , X86ISA::Interrupts
• InitializationPhase : VncServer
• initialized : DiskImage , Event
• Initialized : EventBase
• initializeFlash() : FlashDevice
• initializeMemory() : AbstractNVM , FlashDevice
• initializeStream() : Prefetcher
• initialTemperature() : ThermalDomain
• initialVal : SatCounter
• initiate() : Check , DirectedGenerator , InvalidateGenerator , SeriesRequestGenerator
• initiateAcc() : BaseO3DynInst< Impl > , GPUDynInst , GPUStaticInst , HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::MemFence , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , StaticInst
• initiateAction() : Check
• initiateCheck() : Check
• initiateFetch() : ComputeUnit , FetchUnit
• initiateFlush() : Check
• initiateMemRead() : AtomicSimpleCPU , BaseDynInst< Impl > , BaseSimpleCPU , ExecContext , Minor::ExecContext , SimpleExecContext , TimingSimpleCPU
• initiatePrefetch() : Check
• initiateTranslation() : BaseDynInst< Impl >
• InitInterrupt() : X86ISA::InitInterrupt
• InitMask : EventBase
• initMask : Wavefront
• initMemProxies() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• initNetQueues() : AbstractController
• initNetworkPtr() : AbstractController
• InitrdSize() : LinuxAlphaSystem , LinuxMipsSystem
• InitrdStart() : LinuxAlphaSystem , LinuxMipsSystem
• initSectorTable() : CowDiskImage
• InitStack() : LinuxAlphaSystem , LinuxMipsSystem
• initState() : AlphaProcess , AlphaSystem , ArmFreebsdProcess32 , ArmFreebsdProcess64 , ArmLinuxProcess32 , ArmLinuxProcess64 , ArmProcess32 , ArmProcess64 , ArmSystem , CxxConfigManager , FreebsdArmSystem , FuncPageTable , GenericArmSystem , LinuxAlphaSystem , LinuxArmSystem , LinuxX86System , MipsProcess , MultiLevelPageTable< ISAOps > , PageTableBase , PowerLinuxProcess , PowerProcess , Process , RiscvProcess , Root , SimObject , Sparc32Process , Sparc64Process , SparcProcess , SparcSystem , System , TrafficGen , X86ISA::I386Process , X86ISA::Walker::WalkerState , X86ISA::X86_64Process , X86System
• initStatistics() : ExecStage , ScoreboardCheckStage
• initSummary() : StoreTrace
• InitTc : Intel8254Timer
• initTrafficType() : GarnetSyntheticTraffic
• initTransport() : DistIface , TCPIface
• initVars() : BaseDynInst< Impl > , BaseO3DynInst< Impl >
• initVector : X86ISA::Interrupts
• initVirtMem : Process
• initWithStrOffset() : BaseRegOperand , CRegOperand , DRegOperand , SRegOperand
• injectGlobalMemFence() : ComputeUnit
• injRate : GarnetSyntheticTraffic
• injVnet : GarnetSyntheticTraffic
• inLowPowerState : DRAMCtrl::Rank
• inLSQ : Minor::MinorDynInst
• inMacroop : Minor::Decode::DecodeThreadInfo
• inMemorySystemLimit : Minor::LSQ
• inMissQueue() : BaseCache , BasePrefetcher , Cache
• innerAttrs : ArmISA::TlbEntry
• inNetLink : NetworkInterface
• inNode_ptr : NetworkInterface
• ino_t : RiscvLinux , Solaris
• inp : Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2
• inPrefetch() : QueuedPrefetcher
• input() : Minor::Latch< Data >
• Input() : Minor::Latch< Data >::Input
• inputBuffer : Minor::Decode , Minor::Execute , Minor::Fetch2
• InputBuffer() : Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits >
• inputChar : AlphaAccess , MipsAccess
• InputEvent : BaseRemoteGDB
• inputEvent : BaseRemoteGDB
• InputEvent() : BaseRemoteGDB::InputEvent , GDBListener
• inputEvent : GDBListener
• InputEvent() : GDBListener::InputEvent
• inputFull : X86ISA::I8042
• inputIndex : Minor::Decode::DecodeThreadInfo , Minor::Execute::ExecuteThreadInfo , Minor::Fetch2::Fetch2ThreadInfo
• inputParam1 : UFSHostDevice::UTPUPIUTaskReq
• inputParam2 : UFSHostDevice::UTPUPIUTaskReq
• inputParam3 : UFSHostDevice::UTPUPIUTaskReq
• InputStream() : TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream
• InputUnit() : InputUnit
• inputWire : Minor::Latch< Data >::Input
• inPwrIdleState() : DRAMCtrl::Rank
• inRange() : BaseCache
• inRetry : DmaPort
• inScalarBank() : ArmISA::VfpMacroOp
• insert() : AddrRangeMap< V > , AlphaISA::TLB , ArmISA::TLB , DependencyGraph< DynInstPtr > , EventQueue , flitBuffer , InstructionQueue< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , Minor::LSQ::StoreBuffer , MipsISA::TLB , PowerISA::TLB , QueuedPrefetcher , RiscvISA::TLB , SparcISA::TLB , SparcISA::TlbMap , SymbolTable , Trie< Key, Value > , X86ISA::GpuTLB , X86ISA::TLB
• insert_flit() : OutputUnit
• insertAddr() : MemFootprintProbe
• insertAt() : MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• insertBarrier() : InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl >
• insertBefore() : Event
• insertBlock() : BaseSetAssoc , BaseTags , FALRU , LRU , RandomRepl
• insertCRField() : PowerISA::PowerStaticInst
• insertedLoads : MemDepUnit< MemDepPred, Impl >
• insertedStores : MemDepUnit< MemDepPred, Impl >
• insertFlit() : VirtualChannel
• insertHardBreak() : AlphaISA::RemoteGDB , BaseRemoteGDB
• insertInst() : ROB< Impl >
• insertKernel() : GPUCoalescer
• insertLoad() : LSQ< Impl > , LSQUnit< Impl > , StoreSet
• insertNonSpec() : InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl >
• insertRequest() : GPUCoalescer , Sequencer
• inserts : ArmISA::TLB
• insertScheduledWakeupTime() : Consumer
• insertSoftBreak() : BaseRemoteGDB
• insertStore() : LSQ< Impl > , LSQUnit< Impl > , StoreSet
• insertTableEntry() : ArmISA::TableWalker
• insertThread() : FullO3CPU< Impl >
• inService : QueueEntry
• inst : BaseSimpleCPU , DependencyEntry< DynInstPtr > , InstructionQueue< Impl >::FUCompletion , LSQUnit< Impl >::LSQSenderState , LSQUnit< Impl >::SQEntry , LSQUnit< Impl >::WritebackEvent , MemDepUnit< MemDepPred, Impl >::MemDepEntry , Minor::BranchData , Minor::ExecContext , Minor::LSQ::LSQRequest , Minor::QueuedInst , TimingExprEvalContext
• INST_FETCH : Request
• instAccesses : ArmISA::TLB
• instAddr() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , DefaultCommit< Impl > , FullO3CPU< Impl > , GenericISA::PCStateBase , GPUStaticInst , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , StridePrefetcher::StrideEntry , ThreadContext
• installGlobals() : SparcISA::ISA
• installWindow() : SparcISA::ISA
• instance() : DrainManager , Event , GpuDispatcher , Kvm
• instanceCounter : Event
• instantiate() : CxxConfigManager
• instBytes : X86ISA::Decoder
• InstBytes() : X86ISA::Decoder::InstBytes
• InstCacheMap : X86ISA::Decoder
• instCacheMap : X86ISA::Decoder
• instcount : FullO3CPU< Impl >
• instCyclesSALU : ComputeUnit
• instCyclesVALU : ComputeUnit
• instDone : AlphaISA::Decoder , ArmISA::Decoder , FullO3CPU< Impl > , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• instEffAddr : BaseDynInst< Impl >
• instEventQueue : System
• InstExecInfo() : ElasticTrace::InstExecInfo
• instFetchInstReturned : FetchStage
• instFlags : BaseDynInst< Impl >
• instHits : ArmISA::TLB
• InstId() : Minor::InstId
• InstIntRegOffsets : SparcISA::ISA
• instIsHeadInst() : Minor::Execute
• instIsRightStream() : Minor::Execute
• InstIt : ROB< Impl >
• instLastTick : TraceCPU::FixedRetryGen
• instList : Checker< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl > , ROB< Impl >
• instListIt : BaseDynInst< Impl >
• InstListIt : Checker< Impl >
• instMap : GenericISA::BasicDecodeCache , X86ISA::Decoder
• instMasterID : TraceCPU
• instMisses : ArmISA::TLB
• instMnem : X86ISA::X86MicroopBase
• instName : RiscvISA::UnimplementedFault
• instNum : ElasticTrace::TraceInfo , GPUStaticInst
• inStoreBuffer : Minor::MinorDynInst
• InstPBTrace() : Trace::InstPBTrace
• InstPBTraceRecord : Trace::InstPBTrace , Trace::InstPBTraceRecord
• instPort : BaseKvmCPU
• instQueue : DefaultIEW< Impl >
• InstQueue : DefaultRename< Impl >
• instReady() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• InstRecord() : Trace::InstRecord
• InstRegIndex() : X86ISA::InstRegIndex
• instResult : BaseDynInst< Impl >
• instrExecuted : ExecStage
• instructionBuffer : Wavefront
• instructionBufferHasBranch() : Wavefront
• InstructionCacheMaintenance : ArmISA::ArmFault
• InstructionQueue() : InstructionQueue< Impl >
• instructions : ControlFlowInfo
• insts : DefaultDecode< Impl > , DefaultDecodeDefaultRename< Impl > , DefaultFetchDefaultDecode< Impl > , DefaultIEW< Impl > , DefaultIEWDefaultCommit< Impl > , DefaultRename< Impl > , DefaultRenameDefaultIEW< Impl > , HsaCode , IssueStruct< Impl > , Minor::ForwardInstData , SimPoint::BBInfo
• instsBeingCommitted : Minor::Execute::ExecuteThreadInfo
• instsCommitted : DefaultCommit< Impl >
• instSeqNum : DefaultRename< Impl >::RenameHistory
• instShift : IndirectPredictor
• instShiftAmt : BPredUnit , DefaultBTB
• instsInProgress : DefaultRename< Impl >
• instSize : DefaultFetch< Impl > , GPUStaticInst , HsailISA::HsailGPUStaticInst , KernelLaunchStaticInst
• instsToExecute : InstructionQueue< Impl >
• instsToReplay : MemDepUnit< MemDepPred, Impl >
• instToCommit() : DefaultIEW< Impl >
• instToWaitFor : Minor::MinorDynInst
• instTraceFile : TraceCPU
• InstTracer() : Trace::InstTracer
• instTraceStream : ElasticTrace
• INT_BITS_MAX : Pl390
• INT_BUS_ERROR : HDLcd
• Int_Clear : HDLcd
• INT_LINES_MAX : Pl390
• int_mask : HDLcd
• Int_Mask : HDLcd
• INT_MASK_M : ArmISA::Interrupts
• INT_MASK_P : ArmISA::Interrupts
• INT_MASK_T : ArmISA::Interrupts
• int_rawstat : HDLcd
• Int_RawStat : HDLcd
• Int_Status : HDLcd
• INT_UNDERRUN : HDLcd
• INT_VSYNC : HDLcd
• intAluAccesses : InstructionQueue< Impl >
• IntAssignment() : X86ISA::IntelMP::IntAssignment
• intBase : GenericArmPciHost
• intClear() : HDLcd
• IntClear : PL031 , Sp804::Timer
• intClock() : IGbE
• intConfig : Pl390
• intCount : GenericArmPciHost
• intCtl : Iob
• intDelay : AmbaIntDevice , Pl011
• IntDevice() : X86ISA::IntDevice
• integer : BaseDynInst< Impl >::Result , CheckerCPU::Result , cp::Format
• Intel8254Timer() : Intel8254Timer
• IntelTrace() : Trace::IntelTrace
• IntelTraceRecord() : Trace::IntelTraceRecord
• intEnable : CpuLocalTimer::Timer , Sp804::Timer
• intEnabled : Pl390::BankedRegs , Pl390
• Interal : Iob
• interEvent : IGbE
• interface : EtherLink
• Interface() : EtherLink::Interface , EtherSwitch::Interface
• interface : EtherSwitch::SwitchTableEntry , EtherTapBase , NSGigE , Sinic::Base
• Interface() : Sinic::Interface
• interfaceId : EtherSwitch::Interface
• interfaces : EtherSwitch
• InterfaceTest : X86ISA::I8042
• interleaved() : AddrRange
• intermediateHeader : X86ISA::SMBios::SMBiosTable::SMBiosHeader
• IntermediateHeader() : X86ISA::SMBios::SMBiosTable::SMBiosHeader::IntermediateHeader
• internalMergeFrom() : SubBlock
• internalMergeTo() : SubBlock
• InternalProcReg : AlphaISA::ISA
• interpreter : ElfObject
• Interrupt() : ArchTimer::Interrupt
• interrupt : DefaultCommit< Impl >
• Interrupt : Iob , Minor::BranchData
• interrupt() : RiscvISA::RiscvFault
• interruptDeliveryPending : PciVirtIO
• InterruptLevel() : SparcISA::Interrupts
• InterruptLevelN() : SparcISA::InterruptLevelN
• interruptLine : PCIConfig , PciDevice
• interruptMap : NoMaliGpu
• InterruptMask : ArmISA::Interrupts
• interruptPending : DefaultFetch< Impl > , TimeBufStruct< Impl >::commitComm
• interruptPin : PCIConfig , PciHost::DeviceInterface
• interruptPriority : Minor::Execute
• interrupts : AlphaISA::Interrupts
• Interrupts() : AlphaISA::Interrupts
• interrupts : ArmISA::Interrupts
• Interrupts() : ArmISA::Interrupts , MipsISA::Interrupts , PowerISA::Interrupts , RiscvISA::Interrupts
• interrupts : SparcISA::Interrupts
• Interrupts() : SparcISA::Interrupts , X86ISA::Interrupts
• interruptsPending() : MipsISA::Interrupts
• interruptType : X86ISA::IntelMP::IntAssignment
• intersect() : AddrRangeMap< V > , SparcISA::TlbMap
• intersectionIsEmpty() : NetDest , Set
• intersectionIsNotEmpty() : NetDest
• intersects() : AddrRange , CacheBlk::Lock
• interval : Intel8254Timer::Counter::CounterEvent , MC146818::RTCEvent , MemTest
• intervalCount : SimPoint
• intervalDrift : SimPoint
• intervalSize : SimPoint
• intEvent : Pl011 , Pl050 , Pl111
• IntImmOp() : PowerISA::IntImmOp
• intInstQueueReads : InstructionQueue< Impl >
• intInstQueueWakeupAccesses : InstructionQueue< Impl >
• intInstQueueWrites : InstructionQueue< Impl >
• intLatency : Pl390
• IntLine() : X86ISA::IntLine
• intList : UnifiedFreeList
• intlvBits : AddrRange
• intlvHighBit : AddrRange
• intlvMatch : AddrRange
• intMan : Iob
• intMap : UnifiedRenameMap
• intMask() : HDLcd
• IntMask : PL031
• intMasterId : Request
• intMasterPort : X86ISA::IntDevice
• IntMasterPort() : X86ISA::IntDevice::IntMasterPort
• intNum : AmbaDmaDevice , AmbaIntDevice , Pl011 , Sp804::Timer , UFSHostDevice
• intNumTimer : CpuLocalTimer::Timer
• intNumToBit() : Pl390
• intNumToWord() : Pl390
• intNumWatchdog : CpuLocalTimer::Timer
• IntOp() : PowerISA::IntOp
• intPin : X86ISA::Cmos::X86RTC , X86ISA::I8254
• intPolicy : GenericArmPciHost
• intPriority : Pl390::BankedRegs , Pl390
• intr_flag : AlphaISA::ISA
• intr_sum_type : Malta , Tsunami
• intRaise() : HDLcd
• InTranslation : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• intrBit : Uart8250::IntrEvent
• intrClear() : IdeDisk , PciDevice
• intrClockFrequency : AlphaAccess , MipsAccess
• IntrControl() : IntrControl
• intrctrl : CopyEngineReg::Regs , Platform
• intrDelay : NSGigE , Sinic::Base
• intreg : AlphaISA::AnyReg , ArmISA::AnyReg
• IntReg : BaseO3DynInst< Impl > , ExecContext
• intreg : MipsISA::AnyReg
• IntReg : PhysRegFile
• intreg : PowerISA::AnyReg
• intReg : SparcISA::AnyReg
• IntReg : ThreadContext
• intReg : X86ISA::AnyReg
• intRegFile : PhysRegFile
• intRegfileReads : FullO3CPU< Impl >
• intRegfileWrites : FullO3CPU< Impl >
• IntRegInfo() : ArmV8KvmCPU::IntRegInfo
• intRegMap : ArmISA::ISA , ArmV8KvmCPU , SparcISA::ISA
• intRegs : SimpleThread
• intRenameLookups : DefaultRename< Impl >
• IntrEvent : NSGigE
• intrEvent : NSGigE
• IntrEvent : Sinic::Base
• intrEvent : Sinic::Base
• IntrEvent() : Uart8250::IntrEvent
• IntrEvent::process : NSGigE , Sinic::Base
• intrFreq : AlphaSystem
• IntrMask : Sinic::Device
• IntRotateOp() : PowerISA::IntRotateOp
• intrPending : IdeDisk
• intrPost() : IdeController , IdeDisk , PciDevice
• IntrStatus : Sinic::Device
• intrTick : NSGigE , Sinic::Base
• IntShiftOp() : PowerISA::IntShiftOp
• IntSinkPin() : X86ISA::IntSinkPin
• IntSlavePort() : X86ISA::IntDevice::IntSlavePort
• intSlavePort : X86ISA::Interrupts
• IntSourcePin() : X86ISA::IntSourcePin
• intState() : NoMaliGpu
• intstatus : AlphaISA::Interrupts
• intStatus : ArmISA::Interrupts , HDLcd , IdeController , SparcISA::Interrupts , Uart8250 , Uart
• intWidth : ArmISA::ArmStaticInst
• invAddrLoads : LSQUnit< Impl >
• invAddrSwpfs : LSQUnit< Impl >
• invalid() : ArmISA::TableWalker::L2Descriptor
• Invalid : ArmISA::TableWalker::LongDescriptor
• invalid : SparcISA::PageTableEntry
• invalidate() : BaseSetAssoc , BaseTags , CacheBlk , FALRU , LRU , RandomRepl
• invalidateAll() : X86ISA::GpuTLB
• invalidateBlock() : Cache
• InvalidateGenerator() : InvalidateGenerator
• invalidateMiscReg() : ArmISA::TLB
• invalidateNonGlobal() : X86ISA::GpuTLB
• InvalidateReq : MemCmd
• InvalidateResp : MemCmd
• invalidateSC() : Sequencer
• invalidateVisitor() : Cache
• InvalidCmd : MemCmd
• InvalidDestError : MemCmd
• invalidName : CxxConfigParams
• InvalidOpcode() : X86ISA::InvalidOpcode
• invalidPredictorIndex : TournamentBP
• InvalidTSS() : X86ISA::InvalidTSS
• invariant_regs : ArmKvmCPU
• invCallback() : VIPERCoalescer
• inVisit : CxxConfigManager
• invL1() : VIPERCoalescer
• invldMasterId : Request
• invoke() : AlphaISA::AlphaFault , AlphaISA::ArithmeticFault , AlphaISA::DtbFault , AlphaISA::ItbFault , AlphaISA::ItbPageFault , AlphaISA::NDtbMissFault , ArmISA::AbortFault< T > , ArmISA::ArmFault , ArmISA::ArmSev , ArmISA::FlushPipe , ArmISA::PCAlignmentFault , ArmISA::Reset , ArmISA::SecureMonitorCall , ArmISA::SupervisorCall , ArmISA::SystemError , ArmISA::UndefinedInstruction , ArmISA::VirtualDataAbort , FaultBase , GenericAlignmentFault , GenericISA::M5DebugFault , GenericPageTableFault , MipsISA::AddressFault< T > , MipsISA::CoprocessorUnusableFault , MipsISA::MipsFaultBase , MipsISA::NonMaskableInterrupt , MipsISA::ResetFault , MipsISA::SoftResetFault , MipsISA::TlbFault< T > , ReExec , RiscvISA::RiscvFault , SparcISA::FastDataAccessMMUMiss , SparcISA::FastInstructionAccessMMUMiss , SparcISA::FillNNormal , SparcISA::PowerOnReset , SparcISA::SparcFaultBase , SparcISA::SpillNNormal , SparcISA::TrapInstruction , SyscallRetryFault , UnimpFault , X86ISA::InitInterrupt , X86ISA::InvalidOpcode , X86ISA::PageFault , X86ISA::StartupInterrupt , X86ISA::UnimpInstFault , X86ISA::X86Abort , X86ISA::X86FaultBase , X86ISA::X86Trap
• invoke64() : ArmISA::ArmFault
• invoke_se() : RiscvISA::BreakpointFault , RiscvISA::IllegalFrmFault , RiscvISA::RiscvFault , RiscvISA::SyscallFault , RiscvISA::UnimplementedFault , RiscvISA::UnknownInstFault
• invwbL1() : VIPERCoalescer
• io : Malta , Tsunami
• ioApic : SouthBridge
• IOAPIC() : X86ISA::IntelMP::IOAPIC
• Iob() : Iob
• iobJBusAddr : Iob
• iobJBusSize : Iob
• iobManAddr : Iob
• iobManSize : Iob
• ioctl() : BaseKvmCPU , ClDriver , EmulatedDriver , Kvm , KvmDevice , KvmVM , PerfKvmCounter
• ioctlRun() : BaseKvmCPU
• ioe : Pl111
• ioEnable : NSGigE
• ioEnabled : IdeController
• IOIntAssignment() : X86ISA::IntelMP::IOIntAssignment
• iopt : pdr
• ioptBase : ecoff_fdr
• ioptMax : ecoff_symhdr
• IoSel : RealViewCtrl
• ioShift : IdeController
• iov_base : ArmFreebsd32::tgt_iovec , ArmFreebsd64::tgt_iovec , ArmLinux32::tgt_iovec , ArmLinux64::tgt_iovec , Linux::tgt_iovec , OperatingSystem::tgt_iovec , X86Linux64::tgt_iovec
• iov_len : ArmFreebsd32::tgt_iovec , ArmFreebsd64::tgt_iovec , ArmLinux32::tgt_iovec , ArmLinux64::tgt_iovec , Linux::tgt_iovec , OperatingSystem::tgt_iovec , X86Linux64::tgt_iovec
• ip() : Net::IpAddress
• Ip6Ptr : Net::EthPtr , Net::Ip6Ptr
• IpAddress() : Net::IpAddress
• ipc : ComputeUnit , FullO3CPU< Impl > , Minor::MinorStats , Pl111
• ipdFirst : ecoff_fdr
• ipdInstNum() : GPUStaticInst
• ipdMax : ecoff_symhdr
• ipi_pending : Malta , Tsunami
• ipint : TsunamiCChip
• iplLast : Kernel::Statistics
• iplLastTick : Kernel::Statistics
• IpNetmask() : Net::IpNetmask
• IpPtr : Net::EthPtr , Net::IpPtr
• ipr : AlphaISA::ISA
• iPred : BPredUnit
• IPredEntry() : IndirectPredictor::IPredEntry
• IprEvent() : TimingSimpleCPU::IprEvent
• IpWithPort() : Net::IpWithPort
• IQ : DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , SimpleCPUPolicy< Impl >
• iqBranchInstsIssued : InstructionQueue< Impl >
• iqCount() : DefaultFetch< Impl > , TimeBufStruct< Impl >::iewComm
• iqEntries : DefaultRename< Impl >::FreeEntries
• IqEntry : BaseDynInst< Impl >
• iqFloatInstsIssued : InstructionQueue< Impl >
• iqInstsAdded : InstructionQueue< Impl >
• iqInstsIssued : InstructionQueue< Impl >
• iqIntInstsIssued : InstructionQueue< Impl >
• iqMemInstsIssued : InstructionQueue< Impl >
• iqMiscInstsIssued : InstructionQueue< Impl >
• iqNonSpecInstsAdded : InstructionQueue< Impl >
• iqPolicy : InstructionQueue< Impl >
• IQPolicy : InstructionQueue< Impl >
• iqPtr : InstructionQueue< Impl >::FUCompletion , MemDepUnit< MemDepPred, Impl >
• iqSquashedInstsExamined : InstructionQueue< Impl >
• iqSquashedInstsIssued : InstructionQueue< Impl >
• iqSquashedNonSpecRemoved : InstructionQueue< Impl >
• iqSquashedOperandsExamined : InstructionQueue< Impl >
• irqAsserted : ArmKvmCPU , BaseArmKvmCPU
• irqEnable : Pl390
• irqPhys : GenericTimer::CoreTimers , GenericTimer
• irqVirt : GenericTimer::CoreTimers , GenericTimer
• IRR : X86ISA::I8259
• IRRV : X86ISA::Interrupts
• is_free_signal() : Credit
• is_imm : RegOrImmOperand< RegOperand, T >
• is_stage() : flit
• is_vc_idle() : OutputUnit
• ISA() : AlphaISA::ISA
• isa : ArmISA::BaseISADevice
• ISA() : ArmISA::ISA
• isa : FullO3CPU< Impl >
• ISA() : MipsISA::ISA , PowerISA::ISA , RiscvISA::ISA
• isa : SimpleThread
• ISA() : SparcISA::ISA , X86ISA::ISA
• isAbort : DistIface::Sync
• isAbsolute() : OutputDirectory
• isAcquire() : GPUDynInst , GPUStaticInst , Request
• isAcquireRelease() : GPUDynInst , GPUStaticInst
• isActive() : DmaReadFifo
• IsaFake() : IsaFake
• isAlignmentFault() : AlphaISA::AlignmentFault
• isAllZeros : LSQUnit< Impl >::SQEntry
• isALU() : GPUDynInst , GPUStaticInst
• isArgLoad() : GPUDynInst , GPUStaticInst
• isArgSeg() : GPUDynInst , GPUStaticInst
• isArgSegment() : Request
• isAtCommit() : BaseDynInst< Impl >
• isAtomic() : GPUDynInst , GPUStaticInst , Request
• isAtomicAdd() : GPUDynInst , GPUStaticInst
• isAtomicAnd() : GPUDynInst , GPUStaticInst
• isAtomicCAS() : GPUDynInst , GPUStaticInst
• isAtomicDec() : GPUDynInst , GPUStaticInst
• isAtomicExch() : GPUDynInst , GPUStaticInst
• isAtomicInc() : GPUDynInst , GPUStaticInst
• isAtomicMax() : GPUDynInst , GPUStaticInst
• isAtomicMin() : GPUDynInst , GPUStaticInst
• isAtomicMode() : System
• isAtomicNoRet() : GPUDynInst , GPUStaticInst
• isAtomicNoReturn() : Request
• isAtomicOp() : Packet
• isAtomicOr() : GPUDynInst , GPUStaticInst
• isAtomicRet() : GPUDynInst , GPUStaticInst
• isAtomicReturn() : Request
• isAtomicSub() : GPUDynInst , GPUStaticInst
• isAtomicXor() : GPUDynInst , GPUStaticInst
• isattached() : BaseRemoteGDB
• isAutoDelete() : Event
• isAvailable() : DRAMCtrl::Rank , TraceCPU::ElasticDataGen::HardwareResource
• isBAR() : PciDevice
• isBarrier() : GPUDynInst , GPUStaticInst , Minor::LSQ::BarrierDataRequest , Minor::LSQ::LSQRequest
• isBenign() : X86ISA::X86FaultBase
• isBlockCached() : Packet
• isBlocked() : AbstractController , BaseCache::CacheSlavePort , BaseCache
• isBlockInvalid() : CacheMemory
• isBlockNotBusy() : CacheMemory
• isBranch() : GPUDynInst , GPUStaticInst , Minor::BranchData
• isBroadcast() : NetDest , Set
• isBSYSet() : IdeDisk
• isBubble() : Minor::BranchData , Minor::BubbleIF , Minor::BubbleTraitsAdaptor< ElemType > , Minor::BubbleTraitsPtrAdaptor< PtrType, ElemType > , Minor::ForwardInstData , Minor::ForwardLineData , Minor::MinorDynInst , Minor::NoBubbleTraits< ElemType > , Minor::QueuedInst
• isBusy() : DistEtherLink::LocalIface , EtherInt , EtherLink::Interface , SimpleMemory
• isCachedAbove() : Cache
• isCall() : BaseDynInst< Impl > , StaticInst
• isCC() : StaticInst
• isCCPhysReg() : PhysRegFile
• isClass() : Net::IpOpt
• isCleanEviction() : Packet
• isClockSet() : I2CBus
• isCommitted() : BaseDynInst< Impl >
• isComp() : ElasticTrace::TraceInfo , TraceCPU::ElasticDataGen::GraphNode
• isComplete() : ArmISA::Stage2LookUp , MemChecker::WriteCluster , Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• isCompleted() : BaseDynInst< Impl >
• isCondCtrl() : BaseDynInst< Impl > , StaticInst
• isCondDelaySlot() : BaseDynInst< Impl > , StaticInst
• isCondRegister() : BaseOperand , GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• isCondSwap() : Request
• isConfReported() : AbstractMemory
• isConnected() : BaseMasterPort , BaseSlavePort
• isControl() : BaseDynInst< Impl > , StaticInst
• isCopied() : Net::IpOpt
• isCPUSequencer() : RubyPort
• isDataPrefetch() : BaseDynInst< Impl > , StaticInst
• isDeadlockEventScheduled() : DMASequencer , GPUCoalescer , RubyPort , RubyPortProxy , Sequencer
• isDelayedCommit() : BaseDynInst< Impl > , StaticInst
• isDenormalized() : PowerISA::FloatOp
• isDeviceScope() : GPUDynInst , GPUStaticInst , Request
• isDEVSelect() : IdeDisk
• isDirectCtrl() : BaseDynInst< Impl > , StaticInst
• isDirty() : BaseCache , Cache , CacheBlk , CacheBlkIsDirtyVisitor
• isDiscardable() : Minor::Fetch1::FetchRequest
• isDiskSelected() : IdeController
• isDone() : ComputeUnit
• isDoneSquashing() : ROB< Impl >
• isDrained() : AtomicSimpleCPU , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DrainManager , FullO3CPU< Impl > , FUPool , InstructionQueue< Impl > , LSQ< Impl > , MemDepUnit< MemDepPred, Impl > , Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , Minor::LSQ , Minor::LSQ::StoreBuffer , Minor::Pipeline , TimingSimpleCPU
• isDraining() : FullO3CPU< Impl >
• isDstOperand() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• isElement() : NetDest , Set
• isEmpty() : flitBuffer , LSQ< Impl > , LSQUnit< Impl > , MessageBuffer , NetDest , Queue< Entry > , ROB< Impl > , Set , WriteMask
• isEnabled() : DVFSHandler
• isEnd() : I2CBus
• isEntry() : AlphaISA::StackTrace , ArmISA::StackTrace , BasicBlock , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• isEqual() : NetDest , Set
• isError() : MemCmd
• IsError : MemCmd
• isError() : Packet
• isEviction() : MemCmd
• IsEviction : MemCmd
• isEviction() : Packet
• isExecComplete() : TraceCPU::ElasticDataGen
• isExecuted() : BaseDynInst< Impl >
• isExit() : BasicBlock
• isExitEvent() : Event
• IsExitEvent : EventBase
• isExpressSnoop() : Packet
• isFault() : Minor::ForwardLineData , Minor::MinorDynInst
• isFaultModelEnabled() : GarnetNetwork
• isFetch : ArmISA::TableWalker::WalkerState
• isFile() : OutputDirectory
• isFiltered() : ArmISA::PMU
• isFirstMicroop() : BaseDynInst< Impl > , StaticInst
• isFlagSet() : Event
• isFlat() : GPUDynInst , GPUStaticInst
• isFloating() : BaseDynInst< Impl > , StaticInst
• isFloatPhysReg() : PhysRegFile
• isFlush() : MemCmd
• IsFlush : MemCmd
• isFlush() : Packet
• isForward : MSHR
• isFull() : flitBuffer , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , Queue< Entry > , ROB< Impl > , WriteMask
• isGlbMem() : ComputeUnit
• isGloballyCoherent() : GPUDynInst , GPUStaticInst
• isGlobalMem() : GPUDynInst , GPUStaticInst
• isGlobalSeg() : GPUDynInst , GPUStaticInst
• isGlobalSegment() : Request
• isGmInstruction() : Wavefront
• isGMLdRespFIFOWrRdy() : GlobalMemPipeline
• isGMReqFIFOWrRdy() : GlobalMemPipeline
• isGMStRespFIFOWrRdy() : GlobalMemPipeline
• isGroupSeg() : GPUDynInst , GPUStaticInst
• isGroupSegment() : Request
• isHeadReady() : ROB< Impl >
• isHWPrefetch() : MemCmd
• IsHWPrefetch : MemCmd
• isHyp : ArmISA::TableWalker::WalkerState , ArmISA::TLB , ArmISA::TlbEntry
• isHyperPriv() : SparcISA::ISA
• isIENSet() : IdeDisk
• isInAddrMap() : AbstractMemory
• isInbetweenInsts() : Minor::Execute
• isIncoming() : VirtDescriptor
• isIndirectCtrl() : BaseDynInst< Impl > , StaticInst
• isInfinity() : PowerISA::FloatOp
• isInIQ() : BaseDynInst< Impl >
• isInLSQ() : BaseDynInst< Impl >
• isInROB() : BaseDynInst< Impl >
• isInst() : Minor::MinorDynInst
• isInState() : OutVcState
• isInstDataCpuPort() : RubyTester
• isInstFetch() : Request
• isInstOnlyCpuPort() : RubyTester
• isInstPrefetch() : BaseDynInst< Impl > , StaticInst
• isInteger() : BaseDynInst< Impl > , StaticInst
• isInterrupted() : Minor::Execute
• isIntPhysReg() : PhysRegFile
• IsInvalidate : MemCmd
• isInvalidate() : MemCmd , Packet
• isInvariantReg() : ArmKvmCPU
• isInWriteQueue : DRAMCtrl
• isIprAccess() : BaseDynInst< Impl > , StaticInst
• isIssued() : BaseDynInst< Impl >
• isKernArgSeg() : GPUDynInst , GPUStaticInst
• isKernargSegment() : Request
• isKernel() : Request
• isKvmMap() : AbstractMemory
• isLastMicroop() : BaseDynInst< Impl > , StaticInst
• isLastOpInInst() : Minor::MinorDynInst
• isLeftNode : StackDistCalc::Node
• islistening() : ListenSocket , TCPIface
• IsLlsc : MemCmd
• isLLSC() : MemCmd , Packet , Request
• isLmInstruction() : Wavefront
• isLMReqFIFOWrRdy() : LocalMemPipeline
• isLMRespFIFOWrRdy() : LocalMemPipeline
• isLoad() : BaseDynInst< Impl > , ElasticTrace::TraceInfo , GPUDynInst , GPUStaticInst , LSQUnit< Impl >::LSQSenderState , Minor::LSQ::LSQRequest , StaticInst , TraceCPU::ElasticDataGen::GraphNode
• isLocalMem() : GPUDynInst , GPUStaticInst
• isLocked() : AbstractCacheEntry , CacheMemory , PersistentTable
• isLockedRMW() : Request
• isMachineCheckFault() : MipsISA::MachineCheckFault
• isMacroop() : BaseDynInst< Impl > , StaticInst
• IsMainQueue : EventBase
• isManaged() : Event
• isMarked : StackDistCalc::Node
• isMaster : CxxConfigDirectoryEntry::PortDesc , DistIface
• isMemAddr() : PhysicalMemory , System
• isMemBarrier() : BaseDynInst< Impl > , StaticInst
• isMemFence() : GPUDynInst , GPUStaticInst
• isMemRef() : BaseDynInst< Impl > , GPUDynInst , GPUStaticInst , Minor::MinorDynInst , StaticInst
• isMicroBranch() : BaseDynInst< Impl > , StaticInst
• isMicroop() : BaseDynInst< Impl > , StaticInst
• isMmappedIpr() : Request
• isMMUFault() : ArmISA::AbortFault< T >
• isNan() : PowerISA::FloatOp
• isNegative() : PowerISA::FloatOp
• isNoCostInst() : Minor::MinorDynInst
• isNonPriv() : SparcISA::ISA
• isNonSpeculative() : BaseDynInst< Impl > , StaticInst
• isNoOrder() : GPUDynInst , GPUStaticInst
• isNop() : BaseDynInst< Impl > , GPUDynInst , GPUStaticInst , StaticInst
• isNormalized() : PowerISA::FloatOp
• isNoScope() : GPUDynInst , GPUStaticInst
• isNull() : AbstractMemory
• isNumber() : Net::IpOpt
• isOldestInstALU() : Wavefront
• isOldestInstBarrier() : Wavefront
• isOldestInstFlatMem() : Wavefront
• isOldestInstGMem() : Wavefront
• isOldestInstLMem() : Wavefront
• isOldestInstPrivMem() : Wavefront
• isopt() : Net::TcpOpt
• isOutgoing() : VirtDescriptor
• isOverlap() : WriteMask
• isParallel : H3BloomFilter , MultiBitSelBloomFilter
• isPendingModified() : MSHR
• isPhysMemAddress() : RubyPort::MemSlavePort
• isPipelined() : FuncUnit , FUPool
• isPopable() : Minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits >
• isPrefetch() : MemCmd , Request , StaticInst , WholeTranslationState
• isPresent() : DirectoryMemory , TBETable< ENTRY >
• IsPrint : MemCmd
• isPrint() : MemCmd , Packet
• isPriv : ArmISA::TLB , Request , SparcISA::ISA
• isPrivateSeg() : GPUDynInst , GPUStaticInst
• isPrivateSegment() : Request
• isPseudoOp() : HsailISA::Call
• isPTWalk() : Request
• isQnan() : PowerISA::FloatOp
• isQuiesce() : BaseDynInst< Impl > , StaticInst
• isr : dp_regs
• ISR : X86ISA::I8259
• isRead : DRAMCtrl::DRAMPacket , DramGen
• IsRead : MemCmd
• isRead() : MemCmd , Packet
• isReadable() : CacheBlk
• isReadConflict() : VectorRegisterFile
• isReadOnly : BaseCache , X86ISA::PageTableOps
• isReadOnlySeg() : GPUDynInst , GPUStaticInst
• isReadonlySegment() : Request
• isReady() : flitBuffer , InputUnit , MessageBuffer , NetworkLink , TimerTable , VirtualChannel , WireBuffer
• isReadySrcRegIdx() : BaseDynInst< Impl >
• isref : ThermalNode
• isReferenced() : IniFile::Entry , IniFile::Section
• isRelaxedOrder() : GPUDynInst , GPUStaticInst
• isRelease() : GPUDynInst , GPUStaticInst , Request
• isRequest() : MemCmd
• IsRequest : MemCmd
• isRequest() : Packet
• isReset() : MSHR::TargetList
• isResponse() : MemCmd
• IsResponse : MemCmd
• isResponse() : Packet
• isResultReady() : BaseDynInst< Impl >
• isRetrying() : X86ISA::Walker::WalkerState
• isRetryResp() : LdsState
• isReturn() : BaseDynInst< Impl > , GPUDynInst , GPUStaticInst , StaticInst
• ISRV : X86ISA::Interrupts
• iss() : ArmISA::AbortFault< T > , ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , ArmISA::DataAbort , ArmISA::SecureMonitorCall , ArmISA::SupervisorCall , ArmISA::UndefinedInstruction , AUXU , ecoff_sym , McrMrcMiscInst
• issBase : ecoff_fdr
• isScalar() : GPUDynInst , GPUStaticInst
• isScalarRegister() : BaseOperand , GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• isScoped() : Request
• isSecure : ArmISA::TableWalker::WalkerState , ArmISA::TLB , CacheBlk , Packet , QueueEntry , Request , StridePrefetcher::StrideEntry
• isSerializeAfter() : BaseDynInst< Impl > , StaticInst
• isSerializeBefore() : BaseDynInst< Impl > , StaticInst
• isSerializeHandled() : BaseDynInst< Impl >
• isSerializing() : BaseDynInst< Impl > , StaticInst
• isSet() : AbstractBloomFilter , BlockBloomFilter , BulkBloomFilter , Flags< T > , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter , TimerTable
• issExtMax : ecoff_symhdr
• isShrMem() : ComputeUnit
• isSimdDone() : ComputeUnit
• isSimObject : CxxConfigDirectoryEntry::ParamDesc
• issMax : ecoff_symhdr
• isSnan() : PowerISA::FloatOp
• isSnooping() : AddrMapper , AddrMapper::MapperMasterPort , AtomicSimpleCPU::AtomicCPUDPort , BaseCache::CacheMasterPort , CoherentXBar::CoherentXBarMasterPort , CommMonitor , CommMonitor::MonitorMasterPort , FullO3CPU< Impl >::DcachePort , MasterPort , MemCheckerMonitor , MemCheckerMonitor::MonitorMasterPort , Minor::LSQ::DcachePort , SlavePort , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort
• isSoft() : X86ISA::SoftwareInterrupt , X86ISA::X86FaultBase
• isSpecialOp() : GPUDynInst , GPUStaticInst
• isSpillSeg() : GPUDynInst , GPUStaticInst
• isSpillSegment() : Request
• isSplit : LSQUnit< Impl >::LSQSenderState , LSQUnit< Impl >::SQEntry , WholeTranslationState
• isSquashAfter() : BaseDynInst< Impl > , StaticInst
• isSquashed() : BaseDynInst< Impl > , TimingSimpleCPU
• isSquashedInIQ() : BaseDynInst< Impl >
• isSquashedInLSQ() : BaseDynInst< Impl >
• isSquashedInROB() : BaseDynInst< Impl >
• issRaw : ArmISA::ArmFault
• isSrcOperand() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• isStage2() : ArmISA::AbortFault< T > , ArmISA::ArmFault , ArmISA::TableWalker , ArmISA::TLB
• isStalled() : ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , LSQ< Impl > , LSQUnit< Impl >
• isStallMapEmpty() : MessageBuffer
• isStart() : I2CBus
• isStore() : BaseDynInst< Impl > , ElasticTrace::TraceInfo , GPUDynInst , GPUStaticInst , StaticInst , TraceCPU::ElasticDataGen::GraphNode
• isStoreBlocked : LSQUnit< Impl >
• isStoreConditional() : BaseDynInst< Impl > , StaticInst
• isStreamChange() : Minor::BranchData
• IsStrictlyOrdered : BaseDynInst< Impl >
• isStrictlyOrdered() : Request , TraceCPU::ElasticDataGen::GraphNode , WholeTranslationState
• isSubset() : AddrRange , NetDest , Set
• issue() : MemDepUnit< MemDepPred, Impl > , Minor::Execute
• issue_time : GPUCoalescerRequest , SequencerRequest
• Issued : BaseDynInst< Impl >
• issued() : StoreSet
• issuedMemBarrierInst() : Minor::LSQ
• issuedToMemory : Minor::LSQ::LSQRequest
• issuedTranslationsTable : TLBCoalescer
• issueEvent : GPUCoalescer
• IssueEvent() : GPUCoalescer::IssueEvent
• issueLat : MinorFU
• issueLimit : Minor::Execute
• issueNext() : DMASequencer
• issueNextPrefetch() : Prefetcher
• issuePeriod : ComputeUnit
• issuePipelinedIfetch : DefaultFetch< Impl >
• issuePriority : Minor::Execute
• IssueProbeEvent() : TLBCoalescer::IssueProbeEvent
• issueRate : InstructionQueue< Impl >
• issueRequest() : GlobalMemPipeline , GPUCoalescer , Sequencer
• IssueStruct : DefaultIEW< Impl > , InstructionQueue< Impl > , LSQUnit< Impl > , SimpleCPUPolicy< Impl >
• issueTime : X86ISA::GpuTLB::TranslationState
• issueTLBLookup() : X86ISA::GpuTLB
• issueToExecQueue : DefaultIEW< Impl >
• issueToExecuteDelay : DefaultIEW< Impl >
• issueToExecuteQueue : InstructionQueue< Impl >
• issueTranslation() : X86ISA::GpuTLB
• issueWidth : DefaultIEW< Impl >
• isSuperset() : NetDest , Set
• isSwap() : Request
• isSwitch : DistIface , TCPIface
• IsSWPrefetch : MemCmd
• isSWPrefetch() : MemCmd
• isSyscall() : BaseDynInst< Impl > , StaticInst
• isSystemCoherent() : GPUDynInst , GPUStaticInst
• isSystemScope() : GPUDynInst , GPUStaticInst , Request
• isTagPresent() : CacheMemory , PerfectCacheMemory< ENTRY >
• istatus : ArchTimer
• isTcp : IGbE::TxDescCache
• isTempSerializeAfter() : BaseDynInst< Impl >
• isTempSerializeBefore() : BaseDynInst< Impl >
• isThreadSync() : BaseDynInst< Impl > , StaticInst
• isTiming() : X86ISA::Walker::WalkerState
• isTimingMode : DRAMCtrl , System
• isTouched : CacheBlk , FALRUBlk
• isTraceComplete() : TraceCPU::FixedRetryGen
• isTranslationDelayed() : BaseDynInst< Impl >
• isTtyReq() : AlphaLinux , FreeBSD , Linux , MipsLinux , PowerLinux , SparcLinux
• isUncacheable() : QueueEntry , Request , X86ISA::PageTableOps
• isUncondCtrl() : BaseDynInst< Impl > , StaticInst
• isUnconditionalJump() : GPUDynInst , GPUStaticInst
• isUnmapped() : FuncPageTable , MultiLevelPageTable< ISAOps > , PageTableBase
• isUnverifiable() : BaseDynInst< Impl > , StaticInst
• IsUpgrade : MemCmd
• isUpgrade() : MemCmd , Packet
• isv : ArmISA::DataAbort
• isValid() : CacheBlk , GPUStaticInst , HsailISA::HsailGPUStaticInst , KernelLaunchStaticInst , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement
• isValidCounter() : ArmISA::PMU
• isVecAlu() : ComputeUnit
• isVector : CxxConfigDirectoryEntry::ParamDesc , CxxConfigDirectoryEntry::PortDesc
• isVectorRegister() : BaseOperand , GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• isVlan() : Net::EthHdr
• isVNetOrdered() : GarnetNetwork , SimpleNetwork
• isWaitcnt() : GPUDynInst , GPUStaticInst
• isWavefrontScope() : GPUDynInst , GPUStaticInst , Request
• isWorkgroupScope() : GPUDynInst , GPUStaticInst , Request
• isWorkitemScope() : GPUDynInst , GPUStaticInst
• isWritable() : CacheBlk
• isWrite : ArmISA::TableWalker::WalkerState
• IsWrite : MemCmd
• isWrite() : MemCmd , Packet
• isWriteback() : MemCmd , Packet
• isWriteBarrier() : BaseDynInst< Impl > , StaticInst
• isWriteConflict() : VectorRegisterFile
• isym : AUXU , pdr
• isymBase : ecoff_fdr
• isymMax : ecoff_symhdr
• isZero() : PowerISA::FloatOp
• isZeroReg() : Scoreboard
• itb : CheckerCPU , FullO3CPU< Impl > , SimpleThread
• ItbAcvFault() : AlphaISA::ItbAcvFault
• ItbFault() : AlphaISA::ItbFault
• itBits : ArmISA::Decoder
• ItbPageFault() : AlphaISA::ItbPageFault
• ITBWaitResponse : BaseSimpleCPU
• item : std::deque< T > , std::list< T > , std::vector< T >
• item1 : std::pair< X, Y >
• item2 : std::pair< X, Y >
• items : DecodeCache::AddrMap< Value >::CachePage
• iterator : AddrRangeMap< V >
• Iterator : MSHR
• iterator : PacketFifo , PCEventQueue , QueuedPrefetcher , SparcISA::TlbMap
• Iterator : WriteQueueEntry
• ITickEvent() : TimingSimpleCPU::IcachePort::ITickEvent
• itint : TsunamiCChip
• ITLBPort() : ComputeUnit::ITLBPort
• ItlbWait : DefaultFetch< Impl >
• itLines : Pl390
• itr : iGbReg::Regs
• ittReadRead : CommMonitor::MonitorStats
• ittReqReq : CommMonitor::MonitorStats
• ittWriteWrite : CommMonitor::MonitorStats
• itype_e : Wavefront