Here is a list of all class members with links to the classes they belong to:

- m -

• m : ArmISA::PMU
• M5_ATTR_PACKED : Bitmap , VirtIO9PBase , VirtIOBlock , VirtIOConsole , VirtQueue::VirtRing< T > , VncInput , VncServer
• M5_SC_CLK_TCK : FreeBSD , Linux
• m5_twin32_t() : m5_twin32_t
• m5_twin64_t() : m5_twin64_t
• M5DebugFault() : GenericISA::M5DebugFault
• m5opRange : ArmISA::TLB , ArmSystem
• M5VarArgsFault() : GenericISA::M5VarArgsFault< Func >
• m_abs_cntrl_vec : RubySystem
• m_abstract_controls : RubySystem
• m_access_backing_store : RubySystem
• m_access_mode : Check
• m_AccessMode : RubyRequest
• m_accessModeType : CacheMemory
• m_active_inv_node : InvalidateGenerator
• m_active_node : SeriesRequestGenerator
• m_active_read_node : InvalidateGenerator
• m_adaptive_routing : SimpleNetwork
• m_addr : AccessTraceForAddress , StoreTrace
• m_addr_increment_size : InvalidateGenerator , SeriesRequestGenerator
• m_Address : AbstractCacheEntry
• m_address : Check , InvalidateGenerator , PrefetchEntry , SeriesRequestGenerator , SubBlock
• m_address_profiler_ptr : Profiler
• m_all_instructions : AddressProfiler , Profiler
• m_alloc : DataBlock
• m_array : Prefetcher
• m_assoc : AbstractReplacementPolicy
• m_atomics : AccessTraceForAddress
• m_average_link_utilization : GarnetNetwork
• m_average_vc_load : GarnetNetwork
• m_avg_flit_latency : GarnetNetwork
• m_avg_flit_network_latency : GarnetNetwork
• m_avg_flit_queueing_latency : GarnetNetwork
• m_avg_flit_vnet_latency : GarnetNetwork
• m_avg_flit_vqueue_latency : GarnetNetwork
• m_avg_hops : GarnetNetwork
• m_avg_packet_latency : GarnetNetwork
• m_avg_packet_network_latency : GarnetNetwork
• m_avg_packet_queueing_latency : GarnetNetwork
• m_avg_packet_vnet_latency : GarnetNetwork
• m_avg_packet_vqueue_latency : GarnetNetwork
• m_avg_utilization : Switch
• m_bandwidth_factor : BasicLink
• m_binsize : Histogram
• m_bits : NetDest
• m_block_map : AbstractController
• m_block_size : CacheMemory
• m_block_size_bits : RubySystem
• m_block_size_bytes : CacheRecorder , RubySystem
• m_buf_msgs : MessageBuffer
• m_buffer : flitBuffer
• m_buffer_reads : Router
• m_buffer_size : AbstractController , SimpleNetwork
• m_buffer_writes : Router
• m_buffers_per_ctrl_vc : GarnetNetwork
• m_buffers_per_data_vc : GarnetNetwork
• m_bw_multiplier : SimpleExtLink , SimpleIntLink
• m_bytes_read : CacheRecorder
• m_cache : AbstractReplacementPolicy , CacheMemory , WeightedLRUPolicy
• m_cache_assoc : CacheMemory
• m_cache_num_set_bits : CacheMemory
• m_cache_num_sets : CacheMemory
• m_cache_recorder : RubySystem
• m_cache_size : CacheMemory
• m_check_flush : RubyTester
• m_check_vector : CheckTable
• m_checks_completed : RubyTester
• m_checks_to_complete : RubyTester
• m_checkTable_ptr : RubyTester
• m_clusterID : AbstractController
• m_cntrl_id : TraceRecord
• m_consumer : MessageBuffer
• m_consumer_ptr : Consumer::ConsumerEvent , TimerTable , WireBuffer
• m_contextId : RubyRequest
• m_control_msg_size : Network
• m_controller : Prefetcher , RubyPort
• m_cooldown_enabled : RubySystem
• m_coreId : Sequencer
• m_count : Histogram , LSB_CountingBloomFilter
• m_count_bits : LSB_CountingBloomFilter
• m_credit_count : OutVcState
• m_credit_link : GarnetIntLink , InputUnit , OutputUnit
• m_credit_links : GarnetExtLink
• m_creditlinks : GarnetNetwork
• m_crossbar_activity : CrossbarSwitch , Router
• m_cur_in_port : AbstractController
• m_data : DataBlock , Histogram , SubBlock , TraceRecord
• m_data_address : TraceRecord
• m_data_block_mask : DMASequencer
• m_data_cache_hit_latency : GPUCoalescer , Sequencer
• m_data_msg_size : Network
• m_dataAccessTrace : AddressProfiler
• m_dataCache_ptr : GPUCoalescer , Sequencer
• m_deadlock_check_scheduled : GPUCoalescer , Sequencer
• m_deadlock_threshold : GPUCoalescer , NetworkInterface , RubyTester , Sequencer
• m_DelayedTicks : Message
• m_delayHistogram : AbstractController
• m_delayVCHistogram : AbstractController
• m_demand_accesses : CacheMemory
• m_demand_hits : CacheMemory
• m_demand_misses : CacheMemory
• m_dequeue_callback : MessageBuffer
• m_dequeue_time : flit
• m_description : WireBuffer
• m_directed_tester : DirectedGenerator
• m_direction : InputUnit , OutputUnit
• m_effective_assoc : PseudoLRUPolicy
• m_enable_fault_model : GarnetNetwork
• m_endpoint_bandwidth : SimpleNetwork , Throttle
• m_enqueue_time : flit , VirtualChannel
• m_entries : DirectoryMemory
• m_entry : PerfectCacheLineState< ENTRY >
• m_ext_link_vector : Topology
• m_filter : BlockBloomFilter , BulkBloomFilter , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter
• m_filter_size : BlockBloomFilter , BulkBloomFilter , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter
• m_filter_size_bits : BlockBloomFilter , BulkBloomFilter , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter
• m_first_store : StoreTrace
• m_FirstResponseToCompletionDelayHist : GPUCoalescer , Sequencer
• m_FirstResponseToCompletionDelayHistCoalsr : Profiler
• m_FirstResponseToCompletionDelayHistSeqr : Profiler
• m_flit_network_latency : GarnetNetwork
• m_flit_queueing_latency : GarnetNetwork
• m_flits_injected : GarnetNetwork
• m_flits_received : GarnetNetwork
• m_ForwardToFirstResponseDelayHist : GPUCoalescer , Sequencer
• m_ForwardToFirstResponseDelayHistCoalsr : Profiler
• m_ForwardToFirstResponseDelayHistSeqr : Profiler
• m_fromNetQueues : Network
• m_fully_busy_cycles : AbstractController
• m_gets_sharing_histogram : AddressProfiler
• m_getx_sharing_histogram : AddressProfiler
• m_GPUCoalescer_ptr : GPUCoalescer::GPUCoalescerWakeupEvent
• m_histogram_ptr : AccessTraceForAddress
• m_hitLatencyHist : Sequencer
• m_hitLatencyHistSeqr : Profiler
• m_hitMachLatencyHist : Sequencer
• m_hitMachLatencyHistSeqr : Profiler
• m_hitTypeLatencyHist : Sequencer
• m_hitTypeLatencyHistSeqr : Profiler
• m_hitTypeMachLatencyHist : Sequencer
• m_hitTypeMachLatencyHistSeqr : Profiler
• m_hot_lines : AddressProfiler , Profiler
• m_hw_prefetches : CacheMemory
• m_id : BasicRouter , flit , InputUnit , NetworkInterface , NetworkLink , OutputUnit , OutVcState , VirtualChannel
• m_in : PerfectSwitch , Throttle
• m_in_link : InputUnit
• m_in_ports : AbstractController
• m_IncompleteTimes : Sequencer
• m_IncompleteTimesSeqr : Profiler
• m_InitialToForwardDelayHist : GPUCoalescer , Sequencer
• m_InitialToForwardDelayHistCoalsr : Profiler
• m_InitialToForwardDelayHistSeqr : Profiler
• m_initiatingNode : Check
• m_inports_dirn2idx : RoutingUnit
• m_inports_idx2dirn : RoutingUnit
• m_input_arbiter_activity : SwitchAllocator
• m_input_buffer : VirtualChannel
• m_input_link_id : MessageBuffer
• m_input_unit : Router , SwitchAllocator
• m_inst_cache_hit_latency : Sequencer
• m_inst_profiler_ptr : Profiler
• m_instCache_ptr : GPUCoalescer , Sequencer
• m_int_link_buffers : SimpleNetwork
• m_int_link_vector : Topology
• m_is_blocking : AbstractController
• m_is_free_signal : Credit
• m_is_instruction_only_cache : CacheMemory
• m_is_valid : PrefetchEntry
• m_isCPUSequencer : RubyPort
• m_IssueToInitialDelayHist : GPUCoalescer , Sequencer
• m_IssueToInitialDelayHistCoalsr : Profiler
• m_IssueToInitialDelayHistSeqr : Profiler
• m_largest_bin : Histogram
• m_last_arrival_time : MessageBuffer
• m_last_occ_ptr : WeightedLRUPolicy
• m_last_progress_vector : RubyTester
• m_last_ref_ptr : AbstractReplacementPolicy
• m_last_store : StoreTrace
• m_last_writer : StoreTrace
• m_LastEnqueueTime : Message
• m_latency : BasicLink , BasicRouter , NetworkLink , Router
• m_latencyHist : GPUCoalescer , Sequencer
• m_latencyHistCoalsr : Profiler
• m_latencyHistSeqr : Profiler
• m_LineAddress : RubyRequest
• m_link : LinkOrder
• m_link_bandwidth_multiplier : Throttle
• m_link_latency : Throttle
• m_link_map : Topology
• m_link_order : PerfectSwitch
• m_link_utilization : Throttle
• m_link_utilization_proxy : Throttle
• m_link_utilized : NetworkLink
• m_load_waiting_on_load : Sequencer
• m_load_waiting_on_load_cycles : GPUCoalescer
• m_load_waiting_on_store : Sequencer
• m_load_waiting_on_store_cycles : GPUCoalescer
• m_loads : AccessTraceForAddress
• m_locked : AbstractCacheEntry
• m_lookup_map : CheckTable
• m_machineID : AbstractController
• m_macroBlockAccessTrace : AddressProfiler
• m_mandatory_q_ptr : RubyPort
• m_map : PerfectCacheMemory< ENTRY > , PersistentTable , TBETable< ENTRY > , TimerTable
• m_marked : PersistentTableEntry
• m_masterId : AbstractController
• m_max : Histogram
• m_max_credit_count : OutVcState
• m_max_inv_per_cycle : VIPERCoalescer
• m_max_outstanding_requests : DMASequencer , GPUCoalescer , Sequencer
• m_max_size : MessageBuffer
• m_max_wb_per_cycle : VIPERCoalescer
• m_memory_size_bits : RubySystem
• m_message_queue : WireBuffer
• m_missLatencyHist : GPUCoalescer , Sequencer
• m_missLatencyHistCoalsr : Profiler
• m_missLatencyHistSeqr : Profiler
• m_missMachLatencyHist : GPUCoalescer , Sequencer
• m_missMachLatencyHistCoalsr : Profiler
• m_missMachLatencyHistSeqr : Profiler
• m_missTypeLatencyHist : GPUCoalescer , Sequencer
• m_missTypeLatencyHistCoalsr : Profiler
• m_missTypeLatencyHistSeqr : Profiler
• m_missTypeMachLatencyHist : GPUCoalescer , Sequencer
• m_missTypeMachLatencyHistCoalsr : Profiler
• m_missTypeMachLatencyHistSeqr : Profiler
• m_msg_bytes : SimpleNetwork , Switch , Throttle
• m_msg_counter : Message , MessageBuffer , WireBuffer
• m_msg_counts : SimpleNetwork , Switch , Throttle
• m_msg_ptr : flit
• m_msgs_this_cycle : MessageBuffer
• m_name : DirectoryMemory , TimerTable
• m_negative_filter : Prefetcher
• m_negative_filter_hit : Prefetcher
• m_negative_filter_index : Prefetcher
• m_net_ptr : AbstractController , NetworkInterface
• m_network : RubySystem
• m_network_link : GarnetIntLink
• m_network_links : GarnetExtLink
• m_network_ptr : PerfectSwitch , Router , Switch
• m_networklinks : GarnetNetwork
• m_next_address : TimerTable
• m_next_time : TimerTable
• m_next_valid : TimerTable
• m_ni_flit_size : GarnetNetwork
• m_ni_out_vcs : NetworkInterface
• m_ni_out_vcs_enqueue_time : NetworkInterface
• m_nis : GarnetNetwork
• m_node : Throttle
• m_nodes : Network , Topology
• m_nonunit_filter : Prefetcher
• m_nonunit_hit : Prefetcher
• m_nonunit_index : Prefetcher
• m_nonunit_stride : Prefetcher
• m_not_avail_count : MessageBuffer
• m_nSize : Set
• m_num_buffer_reads : InputUnit
• m_num_buffer_writes : InputUnit
• m_num_cols : GarnetNetwork
• m_num_connected_buffers : SimpleNetwork , Switch
• m_num_cpus : DirectedGenerator , RubyTester
• m_num_directories : DirectoryMemory
• m_num_directories_bits : DirectoryMemory
• m_num_entries : DirectoryMemory
• m_num_hashes : H3BloomFilter , MultiBitSelBloomFilter
• m_num_inports : CrossbarSwitch , SwitchAllocator
• m_num_inst_data_ports : RubyTester
• m_num_inst_only_ports : RubyTester
• m_num_levels : PseudoLRUPolicy
• m_num_nonunit_filters : Prefetcher
• m_num_of_sequencers : AddressProfiler
• m_num_outports : SwitchAllocator
• m_num_readers : Check , CheckTable , RubyTester
• m_num_rows : GarnetNetwork
• m_num_sets : AbstractReplacementPolicy
• m_num_startup_pfs : Prefetcher
• m_num_streams : Prefetcher
• m_num_unit_filters : Prefetcher
• m_num_vcs : CrossbarSwitch , InputUnit , NetworkInterface , OutputUnit , Router , SwitchAllocator
• m_num_vnets : Profiler
• m_num_writers : Check , CheckTable , RubyTester
• m_numa_high_bit : DirectoryMemory
• m_number_of_switches : Topology
• m_number_of_TBEs : AbstractController , TBETable< ENTRY >
• m_occupancy : MessageBuffer
• m_offset : NonCountingBloomFilter
• m_ordered : Network
• m_out : PerfectSwitch , Throttle
• m_out_buffer : OutputUnit
• m_out_link : OutputUnit
• m_out_vc_state : NetworkInterface
• m_outport : flit
• m_outports_dirn2idx : RoutingUnit
• m_outports_idx2dirn : RoutingUnit
• m_output_arbiter_activity : SwitchAllocator
• m_output_port : VirtualChannel
• m_output_unit : CrossbarSwitch , Router , SwitchAllocator
• m_output_vc : VirtualChannel
• m_outstanding_count : DMASequencer , GPUCoalescer , Sequencer
• m_outstanding_inv : VIPERCoalescer
• m_outstanding_wb : VIPERCoalescer
• m_outstandReqHist : GPUCoalescer , Sequencer
• m_outstandReqHistCoalsr : Profiler
• m_outstandReqHistSeqr : Profiler
• m_outvc_state : OutputUnit
• m_packet_network_latency : GarnetNetwork
• m_packet_queueing_latency : GarnetNetwork
• m_packets_injected : GarnetNetwork
• m_packets_received : GarnetNetwork
• m_page_filter : MultiGrainBloomFilter
• m_page_filter_size : MultiGrainBloomFilter
• m_page_filter_size_bits : MultiGrainBloomFilter
• m_page_shift : Prefetcher
• m_par_filter_size : H3BloomFilter , MultiBitSelBloomFilter
• m_par_filter_size_bits : H3BloomFilter , MultiBitSelBloomFilter
• m_pc : Check
• m_pc_address : TraceRecord
• m_pending_message_count : PerfectSwitch
• m_percent_writes : SeriesRequestGenerator
• m_perfect_switch : Switch
• m_Permission : AbstractEntry
• m_permission : PerfectCacheLineState< ENTRY >
• m_phys_mem : RubySystem
• m_PhysicalAddress : RubyRequest
• m_pkt : RubyRequest
• m_port_buffers : Switch
• m_port_requests : SwitchAllocator
• m_Prefetch : RubyRequest
• m_prefetch_cross_pages : Prefetcher
• m_prefetches : CacheMemory
• m_prio_heap : MessageBuffer
• m_priority_rank : MessageBuffer
• m_profiler : AddressProfiler , RubySystem
• m_ProgramCounter : RubyRequest
• m_programCounterAccessTrace : AddressProfiler
• m_randomization : MessageBuffer , RubySystem
• m_readRequestTable : GPUCoalescer , Sequencer
• m_records : CacheRecorder
• m_records_flushed : CacheRecorder
• m_records_read : CacheRecorder
• m_recycle_latency : AbstractController
• m_replacementPolicy_ptr : CacheMemory
• m_request_to_write : PersistentTableEntry
• m_requests_completed : RubyDirectedTester
• m_requests_to_complete : RubyDirectedTester
• m_RequestTable : DMASequencer
• m_resource_stalls : CacheMemory
• m_retryProfileHisto : AddressProfiler
• m_retryProfileHistoRead : AddressProfiler
• m_retryProfileHistoWrite : AddressProfiler
• m_retryProfileMap : AddressProfiler
• m_round_robin_inport : SwitchAllocator
• m_round_robin_invc : SwitchAllocator
• m_round_robin_start : PerfectSwitch
• m_route : flit
• m_router : CrossbarSwitch , InputUnit , OutputUnit , RoutingUnit , SwitchAllocator
• m_router_id : NetworkInterface
• m_routers : GarnetNetwork
• m_routing_algorithm : GarnetNetwork
• m_routing_table : PerfectSwitch , RoutingUnit
• m_routing_unit : Router
• m_ruby_system : BankedArray , Profiler , RubyPort , RubyStatsCallback , RubySystem::RubyEvent , Throttle
• m_runningGarnetStandalone : GPUCoalescer , Sequencer
• m_scheduled_wakeups : Consumer
• m_scope : RubyRequest
• m_sector_bits : BulkBloomFilter
• m_segment : RubyRequest
• m_seq_map : CacheRecorder
• m_sequencer_ptr : Sequencer::SequencerWakeupEvent
• m_set_index : AbstractCacheEntry
• m_sharing : AccessTraceForAddress
• m_sharing_miss_counter : AddressProfiler
• m_size : flit
• m_Size : RubyRequest
• m_size_at_cycle_start : MessageBuffer
• m_size_bits : DirectoryMemory
• m_size_bytes : DirectoryMemory
• m_size_last_time_size_checked : MessageBuffer
• m_skip_bits : MultiBitSelBloomFilter
• m_stage : flit
• m_stall_count : MessageBuffer , NetworkInterface
• m_stall_map_size : MessageBuffer
• m_stall_msg_map : MessageBuffer
• m_stall_queue : NetworkInterface
• m_stall_time : MessageBuffer
• m_start_cycle : RubySystem
• m_start_index_bit : CacheMemory
• m_starving : PersistentTableEntry
• m_status : Check , InvalidateGenerator , SeriesRequestGenerator
• m_store_count : Check , StoreTrace
• m_store_first_to_last : StoreTrace
• m_store_first_to_stolen : StoreTrace
• m_store_last_to_stolen : StoreTrace
• m_store_waiting_on_load : Sequencer
• m_store_waiting_on_load_cycles : GPUCoalescer
• m_store_waiting_on_store : Sequencer
• m_store_waiting_on_store_cycles : GPUCoalescer
• m_stores : AccessTraceForAddress
• m_stores_this_interval : StoreTrace
• m_strict_fifo : MessageBuffer
• m_stride : PrefetchEntry
• m_sumSamples : Histogram
• m_sumSquaredSamples : Histogram
• m_sw_alloc : Router
• m_sw_input_arbiter_activity : Router
• m_sw_output_arbiter_activity : Router
• m_sw_prefetches : CacheMemory
• m_switch : PerfectSwitch , Router , Throttle
• m_switch_buffer : CrossbarSwitch
• m_switch_id : PerfectSwitch , Throttle
• m_switches : SimpleNetwork
• m_systems_to_warmup : RubySystem
• m_tag_index : CacheMemory
• m_temp_filter : BulkBloomFilter
• m_tester_ptr : Check , CheckTable
• m_throttles : Switch
• m_time : flit , Message , OutVcState , TraceRecord
• m_time_last_time_enqueue : MessageBuffer
• m_time_last_time_pop : MessageBuffer
• m_time_last_time_size_checked : MessageBuffer
• m_toNetQueues : Network
• m_topology_ptr : Network
• m_total : AccessTraceForAddress
• m_total_ext_in_link_utilization : GarnetNetwork
• m_total_ext_out_link_utilization : GarnetNetwork
• m_total_hops : GarnetNetwork
• m_total_int_link_utilization : GarnetNetwork
• m_total_samples : StoreTrace
• m_touched_by : AccessTraceForAddress
• m_train_misses : Prefetcher
• m_transitions_per_cycle : AbstractController
• m_trees : PseudoLRUPolicy
• m_type : flit , GPUCoalescerRequest , GPUDynInst , NetworkLink , PrefetchEntry
• m_Type : RubyRequest
• m_type : SequencerRequest , TraceRecord
• m_typeLatencyHist : GPUCoalescer , Sequencer
• m_typeLatencyHistCoalsr : Profiler
• m_typeLatencyHistSeqr : Profiler
• m_uncompressed_trace : CacheRecorder
• m_uncompressed_trace_size : CacheRecorder
• m_unit_filter : Prefetcher
• m_unit_filter_hit : Prefetcher
• m_unit_filter_index : Prefetcher
• m_units_remaining : Throttle
• m_use_time : PrefetchEntry
• m_user : AccessTraceForAddress
• m_usingRubyTester : RubyPort
• m_value : Check , LinkOrder
• m_vc : flit
• m_vc_allocator : NetworkInterface
• m_vc_load : NetworkLink
• m_vc_per_vnet : InputUnit , NetworkInterface , OutputUnit , Router , SwitchAllocator
• m_vc_round_robin : NetworkInterface
• m_vc_state : OutVcState , VirtualChannel
• m_vc_winners : SwitchAllocator
• m_vcs : InputUnit
• m_vcs_per_vnet : GarnetNetwork
• m_version : AbstractController , DirectoryMemory , RubyPort
• m_virtual_networks : Network , NetworkInterface , PerfectSwitch , Router
• m_vnet : flit
• m_vnet_id : MessageBuffer
• m_vnet_type : GarnetNetwork
• m_vnet_type_names : Network
• m_vnets : Throttle
• m_waiting_buffers : AbstractController
• m_wakeup_frequency : RubyTester
• m_wakeups_wo_switch : PerfectSwitch , Throttle
• m_warmup_enabled : RubySystem
• m_way_index : AbstractCacheEntry
• m_weight : BasicLink
• m_weight_table : RoutingUnit
• m_wfid : RubyRequest
• m_writeMask : RubyRequest
• m_writeRequestTable : GPUCoalescer , Sequencer
• m_WTData : RubyRequest
• ma : MSICAP
• macAddr : IGbE
• machine : Linux::utsname , OperatingSystem::utsname , Solaris::utsname
• MachineCheck() : X86ISA::MachineCheck
• MachineCheckFault() : PowerISA::MachineCheckFault
• MachineID() : MachineID
• machineModel : Brig::BrigDirectiveModule
• machInst : ArmISA::ArmFault , ArmISA::HypervisorTrap , ArmISA::SecureMonitorTrap
• MachInst : ArmISA::StackTrace
• machInst : ArmISA::SupervisorTrap
• MachInst : BaseO3DynInst< Impl > , CheckerCPU , DefaultFetch< Impl > , MipsISA::StackTrace , O3CPUImpl , PowerISA::StackTrace , RiscvISA::StackTrace , SimpleThread
• machInst : StaticInst
• MachInst : ThreadContext
• macrocodeBlock : X86ISA::MacroopBase
• MacroMemOp() : ArmISA::MacroMemOp
• macroop : BaseDynInst< Impl > , DefaultFetch< Impl >
• MacroopBase() : X86ISA::MacroopBase
• macroStaticInst : Trace::InstRecord
• MacroVFPMemOp() : ArmISA::MacroVFPMemOp
• magic : aout_exechdr , ecoff_aouthdr , ecoff_symhdr , pcap_file_header
• magic_number : Bitmap::FileHeader
• MagicAtomicNRAddGlobalU32Reg() : HsailISA::Call
• MagicAtomicNRAddGroupU32Reg() : HsailISA::Call
• MagicJoinWFBar() : HsailISA::Call
• MagicLoadGlobalU32Reg() : HsailISA::Call
• MagicMaskLower() : HsailISA::Call
• MagicMaskUpper() : HsailISA::Call
• MagicMostSigBroadcast() : HsailISA::Call
• MagicMostSigThread() : HsailISA::Call
• magicNumber : ProtoStream
• MagicPanic() : HsailISA::Call
• MagicPrefixSum() : HsailISA::Call
• MagicPrintLane() : HsailISA::Call
• MagicPrintLane64() : HsailISA::Call
• MagicPrintWF32() : HsailISA::Call
• MagicPrintWF32ID() : HsailISA::Call
• MagicPrintWF64() : HsailISA::Call
• MagicPrintWFFloat() : HsailISA::Call
• MagicPrintWFID64() : HsailISA::Call
• MagicReduction() : HsailISA::Call
• MagicSimBreak() : HsailISA::Call
• MagicWaitWFBar() : HsailISA::Call
• MagicXactCasLd() : HsailISA::Call
• mainPkt : LSQUnit< Impl >::LSQSenderState
• mainReq : WholeTranslationState
• maintainClusivity() : Cache
• maintInt : VGic
• maintIntPosted : VGic
• majorVer : X86ISA::SMBios::BiosInformation
• majorVersion : X86ISA::SMBios::SMBiosTable::SMBiosHeader
• makeAtomicOpFunctor() : GPUDynInst
• makeAtomicResponse() : Packet
• makeCacheRecorder() : RubySystem
• MakeCallback() : MakeCallback< T, F >
• makeCRField() : PowerISA::FloatOp , PowerISA::IntOp
• makeExtInLink() : GarnetNetwork , Network , SimpleNetwork
• makeExtOutLink() : GarnetNetwork , Network , SimpleNetwork
• makeFragmentPackets() : Minor::LSQ::SplitDataRequest
• makeFragmentRequests() : Minor::LSQ::SplitDataRequest
• makeInternalLink() : GarnetNetwork , Network , SimpleNetwork
• makeLink() : SimpleNetwork , Topology
• makePacket() : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• makeParamsObject() : CxxConfigDirectoryEntry
• makeReadCmd() : Packet
• makeRequest() : DMASequencer , GPUCoalescer , RubyPort , RubyPortProxy , Sequencer , VIPERCoalescer
• makeResponse() : Packet
• makeTimingResponse() : Packet
• makeTopology() : SimpleNetwork
• MakeTsbPtr() : SparcISA::TLB
• makeWriteCmd() : Packet
• Malta() : Malta
• malta : MaltaCChip , MaltaIO , MaltaIO::RTC
• MaltaCChip() : MaltaCChip
• MaltaIO() : MaltaIO
• Managed : EventBase
• Manager : ArmISA::TlbEntry
• manager : ProbeListener , ProbeListenerObject , VectorRegisterFile
• manageReadTransfer() : UFSHostDevice
• manageWriteTransfer() : UFSHostDevice
• manc : iGbReg::Regs
• map() : FuncPageTable , LabelMap , MultiLevelPageTable< ISAOps > , PageTableBase , Process , SimpleRenameMap
• map_t : PCEventQueue
• mapAddressToDirectoryVersion() : DirectoryMemory
• mapAddressToLocalIdx() : DirectoryMemory
• mapAddrToPkt() : GPUCoalescer
• mapIndexToBank() : BankedArray
• MapIter : SparcISA::TLB
• mapPciInterrupt() : GenericArmPciHost , GenericPciHost
• mapper : AddrMapper::MapperMasterPort , AddrMapper::MapperSlavePort
• MapperMasterPort() : AddrMapper::MapperMasterPort
• MapperSlavePort() : AddrMapper::MapperSlavePort
• mapPid() : FreebsdArmSystem , LinuxArmSystem
• MappingFlags : PageTableBase
• mapSize() : ElfObject , ObjectFile
• markCompletedInsts() : DefaultCommit< Impl >
• markDelayed() : ArmISA::Stage2LookUp , ArmISA::Stage2MMU::Stage2Translation , BaseTLB::Translation , DataTranslation< ExecContextPtr > , DefaultFetch< Impl >::FetchTranslation , Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest , TimingSimpleCPU::FetchTranslation , X86ISA::GpuTLB::Translation
• markedPending : MSHR::Target
• markEntries() : PersistentTable
• markInService() : BaseCache , MSHR , MSHRQueue , WriteQueue
• markPending() : MSHRQueue
• markReg() : ConditionRegisterState , VectorRegisterFile
• markRemoved() : GPUCoalescer , Sequencer
• markSrcRegReady() : BaseDynInst< Impl >
• markupInstDests() : Minor::Scoreboard
• markWorkItem() : System
• mask : Iob::IntCtl , LockedAddr , MinorFUTiming
• Mask : MipsISA::PTE
• mask : PixelConverter::Channel
• Mask : PowerISA::PTE , RiscvISA::PTE
• mask : Trie< Key, Value >::Node , UFSHostDevice::taskStart , UFSHostDevice::transferStart , X86ISA::I82094AA
• mask1 : MaltaIO , TsunamiIO
• mask2 : MaltaIO , TsunamiIO
• maskAll() : X86ISA::I8259
• masked : X86ISA::Interrupts
• MaskedISR : PL031 , Sp804::Timer
• maskInt() : Pl011 , PL031
• maskReg : X86ISA::I8237
• masks : X86ISA::Decoder::InstBytes
• maskToPortList() : SnoopFilter
• master : DistIface
• master_ports : RubyPort
• masterId : ArmISA::Stage2MMU , ArmISA::TableWalker , BaseDynInst< Impl >
• masterID : BaseGen
• masterId : BasePrefetcher , CheckerCPU , ComputeUnit , DirectedGenerator , DmaPort , ExternalMaster , GarnetSyntheticTraffic , GpuDispatcher , MemTest , Request , RubyTester
• masterID : TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TrafficGen
• masterId : X86ISA::Walker
• masterIds : System
• masterPort : AddrMapper , Bridge::BridgeSlavePort , Bridge , CommMonitor
• MasterPort() : MasterPort
• masterPort : MemCheckerMonitor , ReqPacketQueue , SerialLink , SerialLink::SerialLinkSlavePort
• MasterPort : SlavePort
• masterPort : SnoopRespPacketQueue
• masterPorts : BaseXBar
• match() : ArmISA::TlbEntry , EmulatedDriver , MinorFUTiming , ObjectMatch
• matches() : CacheBlk::Lock , Trie< Key, Value >::Node
• matchesContext() : LockedAddr
• matchEvent : PL031
• MatchReg : PL031
• matchVal : PL031
• MathExpr() : MathExpr
• MathExprPowerModel() : MathExprPowerModel
• mAtomic : WriteMask
• mAtomicOp : WriteMask
• matrix : LinearSystem
• max : Stats::DistData , Stats::DistStor::Params
• max_bucket : Stats::HistStor
• MAX_BURST_LEN : HDLcd
• Max_CPUs : Malta , Tsunami
• max_creg : HsailCode
• max_dreg : HsailCode
• max_outstanding : HDLcd
• MAX_PIXEL_SIZE : HDLcd
• MAX_PRIO : MathExpr
• max_size : flitBuffer , PollQueue
• max_sreg : HsailCode
• max_track : Stats::DistStor
• max_val : Stats::DistData , Stats::DistStor
• maxAccessesPerRow : DRAMCtrl
• maxAddr : ObjectFile , Pl111
• maxBarCnt : Wavefront
• MaxBits : Trie< Key, Value >
• maxCoalescedReqs : X86ISA::GpuTLB
• maxConf : StridePrefetcher
• maxDependents : TraceCPU::ElasticDataGen
• maxDoorbell : UFSHostDevice::UFSHostDeviceStats
• maxDpVgprs : Wavefront
• maxDynWaveId : Wavefront
• maxEntries : InstructionQueue< Impl > , ROB< Impl >
• maxEntryCount : SnoopFilter
• MaxFlags : BaseDynInst< Impl >
• maxFuncArgsSize : ClDriver
• maxHist : LTAGE
• Maximum_Pri : EventBase
• maximumLatency : PCIConfig
• maximumSize : LdsState
• MaxInstDestRegs : BaseDynInst< Impl > , BaseO3DynInst< Impl > , StaticInst
• MaxInstSrcRegs : BaseDynInst< Impl > , BaseO3DynInst< Impl > , StaticInst
• maxlen : EtherDump
• maxLineWidth : Minor::Fetch1
• maxLoads : MemTest
• maxLQEntries : LSQ< Impl >
• maxMasters() : System
• maxMemorySlot : KvmVM
• maxNumDependents : ElasticTrace
• maxOpLatencies : FUPool
• maxOutstandingDma : Pl111
• maxPeriod : LinearGen , RandomGen
• maxPhysicalRegs : DefaultRename< Impl >
• maxPhysRegDepMapSize : ElasticTrace
• maxPID : System
• maxReadyListSize : TraceCPU::ElasticDataGen
• maxRegIdx : CRegOperand , DRegOperand , SRegOperand
• maxReqSize : DmaReadFifo
• maxRobDep : TraceCPU::ElasticDataGen::GraphNode
• maxSeqCountPerRank : DramRotGen
• maxsize() : PacketFifo
• maxSpVgprs : Wavefront
• maxSQEntries : LSQ< Impl >
• maxTempStoreSize : ElasticTrace
• MaxThreads : O3CPUImpl
• maxVal : SatCounter
• maxVnicDistance : Sinic::Device
• MaxWidth : O3CPUImpl
• mb : PowerISA::IntRotateOp
• mc : MSICAP
• MC146818() : MC146818
• MciCtl : RealViewCtrl
• MCR : Uart8250
• McrMrcMiscInst() : McrMrcMiscInst
• McrrOp() : McrrOp
• md : MSICAP
• md5() : Net::TcpOpt
• mday : MC146818
• mdic : iGbReg::Regs
• me : PowerISA::IntRotateOp
• meanDistance : X86ISA::GpuTLB::AccessInfo
• mear : dp_regs
• MediaOpBase() : X86ISA::MediaOpBase
• MediaOpImm() : X86ISA::MediaOpImm
• MediaOpReg() : X86ISA::MediaOpReg
• mem : CallArgMem
• mem2hex() : BaseRemoteGDB
• mem_size : AlphaAccess , MipsAccess
• MEM_SWAP : Request
• MEM_SWAP_COND : Request
• mem_unit : AlphaLinux::tgt_sysinfo , ArmLinux32::tgt_sysinfo , ArmLinux64::tgt_sysinfo , MipsLinux::tgt_sysinfo , Sparc32Linux::tgt_sysinfo , SparcLinux::tgt_sysinfo , X86Linux32::tgt_sysinfo , X86Linux64::tgt_sysinfo
• mem_valid : Trace::InstRecord
• memAccess() : BaseO3DynInst< Impl >
• memAccessFlags : ArmISA::Memory64 , ArmISA::MicroMemOp , ArmISA::MicroMemPairOp , ArmISA::MicroNeonMemOp , PowerISA::MemOp
• memAccInst() : StaticInst
• memAccPtr : PowerISA::MemOp
• memAddr() : GenericPciHost , PciHost::DeviceInterface , PciHost
• memAllocCounter : DependencyGraph< DynInstPtr >
• memAttr() : ArmISA::TableWalker::LongDescriptor
• memAttrs() : ArmISA::TableWalker
• memAttrsAArch64() : ArmISA::TableWalker
• memAttrsLPAE() : ArmISA::TableWalker
• members : ClockDomain
• MemChecker() : MemChecker
• memchecker : MemCheckerMonitor
• MemCheckerMonitor() : MemCheckerMonitor
• MemCheckerMonitorSenderState() : MemCheckerMonitor::MemCheckerMonitorSenderState
• MemCmd() : MemCmd
• MemCompleteEvent : GarnetSyntheticTraffic
• memData : BaseDynInst< Impl >
• MemDepEntry() : MemDepUnit< MemDepPred, Impl >::MemDepEntry
• MemDepEntryPtr : MemDepUnit< MemDepPred, Impl >
• memDepHash : MemDepUnit< MemDepPred, Impl >
• MemDepHash : MemDepUnit< MemDepPred, Impl >
• MemDepHashIt : MemDepUnit< MemDepPred, Impl >
• memDepReady : MemDepUnit< MemDepPred, Impl >::MemDepEntry
• MemDepUnit : InstructionQueue< Impl >
• memDepUnit : InstructionQueue< Impl >
• MemDepUnit() : MemDepUnit< MemDepPred, Impl > , SimpleCPUPolicy< Impl >
• memDepViolator : LSQUnit< Impl >
• MemDispOp() : PowerISA::MemDispOp
• MemFence() : HsailISA::MemFence
• memFenceMemOrder : HsailISA::MemFence
• MemFenceReq : MemCmd
• MemFenceResp : MemCmd
• memFenceScopeSegGlobal : HsailISA::MemFence
• memFenceScopeSegGroup : HsailISA::MemFence
• memFenceScopeSegImage : HsailISA::MemFence
• memFlags : X86ISA::MemOp
• MemFootprintProbe() : MemFootprintProbe
• MemInst() : HsailISA::MemInst
• memInvalidate() : BaseCache , BaseTLB , Cache , SimObject
• memMasterPort : RubyPort
• MemMasterPort() : RubyPort::MemMasterPort
• MemObject() : MemObject
• MemOp() : PowerISA::MemOp , X86ISA::MemOp
• memOpDone() : BaseDynInst< Impl >
• MemOpDone : BaseDynInst< Impl >
• memOpDone() : BaseDynInst< Impl >
• memOpsPred : StoreSet
• memOrderViolationEvents : DefaultIEW< Impl >
• memories : PhysicalMemory
• Memory() : ArmISA::Memory
• memory : DRAMCtrl::MemoryPort , DRAMCtrl::Rank , DRAMSim2::MemoryPort , SimpleMemory::MemoryPort
• Memory64() : ArmISA::Memory64
• memoryCommitLimit : Minor::Execute
• MemoryDImm() : ArmISA::MemoryDImm
• MemoryDImm64() : ArmISA::MemoryDImm64
• MemoryDImmEx64() : ArmISA::MemoryDImmEx64
• MemoryDReg() : ArmISA::MemoryDReg
• MemoryEx64() : ArmISA::MemoryEx64
• MemoryExDImm() : ArmISA::MemoryExDImm
• MemoryExImm() : ArmISA::MemoryExImm
• MemoryImm() : ArmISA::MemoryImm
• MemoryImm64() : ArmISA::MemoryImm64
• memoryIssueLimit : Minor::Execute
• MemoryLiteral64() : ArmISA::MemoryLiteral64
• memoryMode : System
• MemoryNeedsRetry : Minor::LSQ
• MemoryOffset() : ArmISA::MemoryOffset< Base >
• memoryOrder : Brig::BrigInstAtomic , Brig::BrigInstMemFence , Brig::BrigInstQueue , Brig::BrigInstSignal , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType >
• memoryPort : AbstractController
• MemoryPort() : AbstractController::MemoryPort , DRAMCtrl::MemoryPort , DRAMSim2::MemoryPort , SimpleMemory::MemoryPort
• MemoryPostIndex() : ArmISA::MemoryPostIndex< Base >
• MemoryPostIndex64() : ArmISA::MemoryPostIndex64
• MemoryPreIndex() : ArmISA::MemoryPreIndex< Base >
• MemoryPreIndex64() : ArmISA::MemoryPreIndex64
• MemoryRaw64() : ArmISA::MemoryRaw64
• MemoryReg() : ArmISA::MemoryReg
• MemoryReg64() : ArmISA::MemoryReg64
• MemoryRunning : Minor::LSQ
• memoryScope : Brig::BrigInstAtomic , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType >
• MemorySegment : HsaCode
• memorySlots : KvmVM
• MemoryState : Minor::LSQ
• MemoryType : ArmISA::TlbEntry
• memPort : ComputeUnit
• memProxy : VirtDescriptor , VirtQueue
• memReadCallback : UFSHostDevice , UFSHostDevice::UFSSCSIDevice
• memReq : CheckerCPU , DefaultFetch< Impl >
• MemReqEvent() : ComputeUnit::DataPort::MemReqEvent
• memReqFlags : BaseDynInst< Impl >
• memReqsInPipe : Wavefront
• MemRespEvent() : ComputeUnit::DataPort::MemRespEvent
• memSchedPolicy : DRAMCtrl
• memsetBlob() : FSTranslatingPortProxy , PortProxy , SETranslatingPortProxy
• memSidePort : BaseCache
• MemSidePort() : Cache::MemSidePort
• memSidePort : TLBCoalescer
• MemSidePort() : TLBCoalescer::MemSidePort
• memSidePort : X86ISA::GpuTLB
• MemSidePort() : X86ISA::GpuTLB::MemSidePort
• memSize() : AtagMem , System
• memSlavePort : RubyPort
• MemSlavePort() : RubyPort::MemSlavePort
• MemSlot() : KvmVM::MemSlot
• MemSpaceConfigFlags : Request
• MemSpaceConfigFlagsType : Request
• memStart() : AtagMem
• MemState() : MemState
• memState : Process
• memStatusVector : GPUDynInst
• memtest : MemTest::CpuPort
• MemTest() : MemTest
• memTraceBusy : Wavefront
• MemTraceProbe() : MemTraceProbe
• memType : HsailISA::HsailDataType< _OperandType, _CType, _memType, _vgprType, IsBits >
• memWriteback() : BaseCache , Cache , MinorCPU , RubySystem , SimObject
• memWriteCallback : UFSHostDevice::UFSSCSIDevice
• merge() : AbstractBloomFilter , BlockBloomFilter , BulkBloomFilter , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter , X86ISA::X86StaticInst
• mergedWrBursts : DRAMCtrl
• mergeFrom() : SubBlock
• mergesWith() : AddrRange
• mergeTe() : ArmISA::Stage2LookUp
• mergeTo() : SubBlock
• message : CxxConfigManager::Exception , GenericISA::M5DebugFault , I2CBus
• Message() : Message
• message : UFSHostDevice::SCSIReply
• MessageBuffer() : MessageBuffer
• MessageMasterPort() : MessageMasterPort
• MessageReq : MemCmd
• MessageResp : MemCmd
• MessageSizeType_to_int() : Network
• MessageSlavePort() : MessageSlavePort
• method : Stats::MethodProxy< T, V > , Stats::ValueBase< Derived >
• MethodPointer : Stats::MethodProxy< T, V >
• MethodProxy() : Stats::MethodProxy< T, V >
• mibc : dp_regs
• MicrocodeRom() : X86ISAInst::MicrocodeRom
• MicroIntImmOp() : ArmISA::MicroIntImmOp
• MicroIntImmXOp() : ArmISA::MicroIntImmXOp
• MicroIntMov() : ArmISA::MicroIntMov
• MicroIntOffset : SparcISA::ISA
• MicroIntOp() : ArmISA::MicroIntOp
• MicroIntRegOp() : ArmISA::MicroIntRegOp
• MicroIntRegXOp() : ArmISA::MicroIntRegXOp
• MicroMemOp() : ArmISA::MicroMemOp
• MicroMemPairOp() : ArmISA::MicroMemPairOp
• MicroNeonMemOp() : ArmISA::MicroNeonMemOp
• MicroNeonMixLaneOp() : ArmISA::MicroNeonMixLaneOp
• MicroNeonMixLaneOp64() : ArmISA::MicroNeonMixLaneOp64
• MicroNeonMixOp() : ArmISA::MicroNeonMixOp
• MicroNeonMixOp64() : ArmISA::MicroNeonMixOp64
• MicroOp() : ArmISA::MicroOp
• microOpCount : TraceCPU::ElasticDataGen::InputStream
• microopPC : Minor::Decode::DecodeThreadInfo
• microOps : ArmISA::PredMacroOp
• microops : X86ISA::MacroopBase
• MicroOpX() : ArmISA::MicroOpX
• microPC() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , DefaultCommit< Impl > , FullO3CPU< Impl > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::PCStateBase , GenericISA::UPCState< MachInst > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• microseconds : pcap_pkthdr
• MicroSetPCCPSR() : ArmISA::MicroSetPCCPSR
• mid : MSICAP
• MightBeMicro() : ArmISA::MightBeMicro
• MightBeMicro64() : ArmISA::MightBeMicro64
• min : MC146818 , Stats::DistData , Stats::DistStor::Params
• min_alrm : MC146818
• min_bucket : Stats::HistStor
• min_track : Stats::DistStor
• min_val : Stats::DistData , Stats::DistStor
• minAllocatedElements() : SimplePoolManager
• minAllocation() : PoolManager
• minBankPrep() : DRAMCtrl
• minConf : StridePrefetcher
• minHist : LTAGE
• Minimum_Pri : EventBase
• minimumCommitCycle : Minor::MinorDynInst
• minimumGrant : PCIConfig
• MinorActivityRecorder() : Minor::MinorActivityRecorder
• MinorBuffer() : Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits >
• MinorCPU() : MinorCPU
• MinorCPUPort() : MinorCPU::MinorCPUPort
• MinorDynInst() : Minor::MinorDynInst
• MinorFU() : MinorFU
• MinorFUPool() : MinorFUPool
• MinorFUTiming() : MinorFUTiming
• MinorOpClass() : MinorOpClass
• MinorOpClassSet() : MinorOpClassSet
• MinorStats() : Minor::MinorStats
• minorTrace() : Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Latch< Data > , Minor::LSQ , Minor::LSQ::StoreBuffer , Minor::MinorActivityRecorder , Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Pipeline , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , Minor::Scoreboard
• minorTraceInst() : Minor::MinorDynInst
• minorTraceResponseLine() : Minor::Fetch1
• minorVer : X86ISA::SMBios::BiosInformation
• minorVersion : X86ISA::SMBios::SMBiosTable::SMBiosHeader
• minPeriod : LinearGen , RandomGen
• minTagWidth : LTAGE
• minWritesPerSwitch : DRAMCtrl
• Mips : ObjectFile
• MipsLinuxProcess() : MipsLinuxProcess
• MipsProcess() : MipsProcess
• MipsSystem() : MipsSystem
• Misc : RealViewCtrl
• MiscOp() : PowerISA::MiscOp
• MiscReg : BaseO3DynInst< Impl > , CheckerCPU , ExecContext
• miscReg : McrMrcMiscInst
• MiscReg : SimpleExecContext , SimpleThread , ThreadContext
• miscRegContext : ArmISA::TLB
• miscRegFile : MipsISA::ISA , RiscvISA::ISA
• miscRegFile_WriteMask : MipsISA::ISA
• miscRegfileReads : FullO3CPU< Impl >
• miscRegfileWrites : FullO3CPU< Impl >
• miscRegIdMap : ArmV8KvmCPU
• miscRegIdxs : CheckerCPU
• MiscRegInfo() : ArmV8KvmCPU::MiscRegInfo
• miscRegMap : ArmV8KvmCPU
• miscRegNames : MipsISA::ISA , RiscvISA::ISA
• MiscRegRegImmOp() : MiscRegRegImmOp
• miscRegs : ArmISA::ISA , PowerISA::ISA
• MiscRegSwitch : ArmISA::ISA
• miscRegValid : ArmISA::TLB
• mispredicted() : BaseDynInst< Impl >
• mispredictInst : DefaultIEWDefaultCommit< Impl > , TimeBufStruct< Impl >::commitComm , TimeBufStruct< Impl >::decodeComm
• mispredPC : DefaultIEWDefaultCommit< Impl > , TimeBufStruct< Impl >::decodeComm
• misrouting : FaultModel
• MISS_RETURN : X86ISA::GpuTLB
• missCount : BaseCache
• misses : ArmISA::TLB , BaseCache , FALRU , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• missLatency : BaseCache
• missLatency1 : X86ISA::GpuTLB
• missLatency2 : X86ISA::GpuTLB
• missRate : BaseCache
• mmap() : EmulatedDriver , Shader
• mmapFlagTable : ArmLinux64 , SparcSolaris , X86Linux32
• mmapGrowsDown() : AlphaProcess , Process , RiscvProcess
• MMAPPED_IPR : Request
• mmapPerf() : PerfKvmCounter
• mmapUsingNoReserve : PhysicalMemory
• mmask : MSICAP
• mMask : WriteMask
• MmDisk() : MmDisk
• mmioRing : BaseKvmCPU
• mmx : Trace::X86NativeTrace::ThreadState
• mnem : X86ISA::X86FaultBase
• mnemonic : ArmISA::UndefinedInstruction , StaticInst , X86ISA::X86FaultBase
• mod : X86ISA::IntelMP::CompatAddrSpaceMod
• mode() : AlphaISA::Kernel::Statistics , ArmISA::RfeOp , ArmISA::SrsOp , ArmISA::Stage2LookUp , ArmISA::TableWalker::WalkerState
• Mode : BaseTLB
• mode : Intel8254Timer::Counter , Intel8254Timer , WholeTranslationState , X86ISA::Decoder , X86ISA::ExtMachInst
• Mode : X86ISA::GpuTLB
• mode : X86ISA::I8259 , X86ISA::Walker::WalkerState
• mode1 : MaltaIO , TsunamiIO
• mode2 : MaltaIO , TsunamiIO
• mode_t : RiscvLinux , Solaris
• ModeVal : Intel8254Timer
• modifier : Brig::BrigDirectiveExecutable , Brig::BrigDirectiveFbarrier , Brig::BrigDirectiveVariable , Brig::BrigInstCmp , Brig::BrigInstCvt , Brig::BrigInstMem , Brig::BrigInstMod , Brig::BrigInstSegCvt
• modpath : EmbeddedPython
• modRM : X86ISA::ExtMachInst
• ModRMState : X86ISA::Decoder
• mon : CommMonitor::MonitorMasterPort , CommMonitor::MonitorSlavePort , MC146818 , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor::MonitorSlavePort
• MonitorMasterPort() : CommMonitor::MonitorMasterPort , MemCheckerMonitor::MonitorMasterPort
• MonitorSlavePort() : CommMonitor::MonitorSlavePort , MemCheckerMonitor::MonitorSlavePort
• MonitorStats() : CommMonitor::MonitorStats
• moreBytes() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• moreToWb : IGbE::DescCache< T >
• mouse : VncInput , X86ISA::I8042
• mouseAt() : Pl050 , VncMouse
• MouseEvents : VncServer
• mouseFullInt : X86ISA::I8042
• mouseIntPin : X86ISA::I8042
• MouseLeftButton : VncServer
• MouseMiddleButton : VncServer
• mouseOutputFull : X86ISA::I8042
• MouseRightButton : VncServer
• moveFromRequestsToTransfers() : Minor::Fetch1 , Minor::LSQ
• moveToFront() : MSHRQueue
• moveToHead() : CacheSet< Blktype > , FALRU
• moveToReady() : MemDepUnit< MemDepPred, Impl >
• moveToTail() : CacheSet< Blktype >
• moveToYoungerInst() : InstructionQueue< Impl >
• mpba : MSIXCAP
• mpConfigTable : X86System
• mpend : MSICAP
• mpFloatingPointer : X86System
• MrrcOp() : MrrcOp
• MrsOp() : MrsOp
• MSB : Intel8254Timer::Counter
• MsbOnly : Intel8254Timer
• msec() : Time
• msg_data : MSIXTable
• MsgBufType : AbstractController
• msgSize : UFSHostDevice::SCSIReply
• msgType : DistHeaderPkt::Header
• MsgType : DistHeaderPkt , DistIface
• MsgVecType : AbstractController
• MSHR() : MSHR
• mshr_hits : BaseCache
• mshr_miss_latency : BaseCache
• mshr_misses : BaseCache
• mshr_uncacheable : BaseCache
• mshr_uncacheable_lat : BaseCache
• mshrMissRate : BaseCache
• mshrQueue : BaseCache
• MSHRQueue : MSHR , MSHRQueue
• MSHRQueue_MSHRs : BaseCache
• MSHRQueue_WriteBuffer : BaseCache
• MSHRQueueIndex : BaseCache
• MSI_SETSPI_NSR : Gicv2m
• MSI_TYPER : Gicv2m
• msicap : PciDevice
• MSICAP_BASE : PciDevice
• msix_pba : PciDevice
• MSIX_PBA_END : PciDevice
• MSIX_PBA_OFFSET : PciDevice
• msix_table : PciDevice
• MSIX_TABLE_END : PciDevice
• MSIX_TABLE_OFFSET : PciDevice
• msixcap : PciDevice
• MSIXCAP_BASE : PciDevice
• MSIXCAP_ID_OFFSET : PciDevice
• MSIXCAP_MPBA_OFFSET : PciDevice
• MSIXCAP_MTAB_OFFSET : PciDevice
• MSIXCAP_MXC_OFFSET : PciDevice
• mSize : WriteMask
• msr : PowerISA::RemoteGDB::PowerGdbRegCache
• MsrBase() : MsrBase
• MsrImmOp() : MsrImmOp
• MsrRegOp() : MsrRegOp
• mss() : Net::TcpOpt
• mState : Trace::ArmNativeTrace , Trace::X86NativeTrace
• mtab : MSIXCAP
• mtup() : Net::IpOpt
• mtur() : Net::IpOpt
• mtype : ArmISA::TlbEntry
• mua : MSICAP
• Mult3() : ArmISA::Mult3
• Mult4() : ArmISA::Mult4
• multHi() : X86ISA::MediaOpBase
• MultiBitSelBloomFilter() : MultiBitSelBloomFilter
• multicast() : Net::EthAddr
• multicastHashEnable : NSGigE
• MultiGrainBloomFilter() : MultiGrainBloomFilter
• MultiLevelPageTable() : MultiLevelPageTable< ISAOps >
• multiProc : ArmSystem
• multiThread : System
• mults_list : H3BloomFilter
• MustBeOne : ArmISA::TLB
• mustCheckAbove() : Packet
• mustRetry : StubSlavePort
• mustSendRetry : BaseCache::CacheSlavePort
• MuxingKvmGic() : MuxingKvmGic
• mwait() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• mwaitAtomic() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• mxc : MSIXCAP
• mxcsr : FXSave
• mxcsr_mask : FXSave
• mxid : MSIXCAP
• myname : Kernel::Statistics
• mystream : Stats::Text