Here is a list of all class members with links to the classes they belong to:

- r -

• r : AlphaISA::RemoteGDB::AlphaGdbRegCache , ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , MathExpr::Node , MipsISA::RemoteGDB::MipsGdbRegCache , PowerISA::RemoteGDB::PowerGdbRegCache , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , Stats::BinaryNode< Op > , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache
• r10 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• r11 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• r12 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• r13 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• r14 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• r15 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• r8 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• r9 : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• radv : iGbReg::Regs
• radvEvent : IGbE
• radvProcess() : IGbE
• raise() : X86ISA::IntSourcePin
• raiseInterrupt() : ArmISA::PMU
• raiseInterruptPin() : X86ISA::I82094AA , X86ISA::I8259 , X86ISA::IntDevice
• raiseInterrupts() : Pl011
• Random() : Random
• random() : Random
• RandomGen() : RandomGen
• randomPriority() : MinorCPU
• RandomRepl() : RandomRepl
• range : AbstractMemory , BackingStoreEntry , BaseXBar::PortCache , LdsState , SparcISA::TlbEntry
• range_t : PCEventQueue
• RangeAddrMapper() : RangeAddrMapper
• rangeCache : PhysicalMemory
• rangeList : X86ISA::IntelMP::CompatAddrSpaceMod
• RangeMap : AddrRangeMap< V > , SparcISA::TlbMap
• rangeMRU : ArmISA::TLB
• ranges : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• rank : DistIface , DRAMCtrl::DRAMPacket , DRAMCtrl::Rank
• Rank() : DRAMCtrl::Rank
• rank : TCPIface::NodeInfo
• rankBits : DramGen
• RankDumpCallback() : DRAMCtrl::RankDumpCallback
• rankParam() : DistIface
• rankRef : DRAMCtrl::DRAMPacket
• ranks : DRAMCtrl::RankDumpCallback , DRAMCtrl
• ranksPerChannel : DRAMCtrl
• RAS : BPredUnit
• RASIncorrect : BPredUnit
• RASIndex : BPredUnit::PredictorHistory
• RASTarget : BPredUnit::PredictorHistory
• RateGen : Intel8254Timer
• RawDiskImage() : RawDiskImage
• rawInt : Pl011 , PL031 , Sp804::Timer
• rawIntTimer : CpuLocalTimer::Timer
• rawIntWatchdog : CpuLocalTimer::Timer
• RawISR : PL031 , Sp804::Timer
• RawObject() : RawObject
• rawResetWatchdog : CpuLocalTimer::Timer
• rax : Trace::X86NativeTrace::ThreadState , X86ISA::CpuidResult , X86ISA::RemoteGDB::AMD64GdbRegCache
• rbp : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• rbx : Trace::X86NativeTrace::ThreadState , X86ISA::CpuidResult , X86ISA::RemoteGDB::AMD64GdbRegCache
• rcSet : PowerISA::FloatOp , PowerISA::IntOp
• rctl : iGbReg::Regs
• rcx : Trace::X86NativeTrace::ThreadState , X86ISA::CpuidResult , X86ISA::RemoteGDB::AMD64GdbRegCache
• rdba : iGbReg::Regs
• rdGmReqsInPipe : Wavefront
• rdh : iGbReg::Regs
• rdi : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• rdlen : iGbReg::Regs
• rdLmReqsInPipe : Wavefront
• rdmces : PAL
• rdPerTurnAround : DRAMCtrl
• rdps : PAL
• rdQLenPdf : DRAMCtrl
• rdt : iGbReg::Regs
• rdtr : iGbReg::Regs
• rdtrEvent : IGbE
• rdtrProcess() : IGbE
• rdunique : PAL
• rdusp : PAL
• rdval : PAL
• rdx : Trace::X86NativeTrace::ThreadState , X86ISA::CpuidResult , X86ISA::RemoteGDB::AMD64GdbRegCache
• rdy() : WaitClass
• read() : A9SCU , AlphaBackdoor , AmbaFake , BadDevice , BaseRemoteGDB
• Read : BaseTLB
• read() : CircleBuf< T > , ConditionRegisterState , CopyEngine::CopyEngineChannel , CopyEngine , CowDiskImage , CpuLocalTimer , CpuLocalTimer::Timer , DiskImage
• READ : DRAMCtrl
• read() : DumbTOD , EnergyCtrl , Fifo< T > , FullO3CPU< Impl > , GenericPciHost , GenericTimerMem , Gicv2m , GpuDispatcher , HDLcd , I2CBus , I2CDevice , IdeController , IGbE , Intel8254Timer::Counter , Iob , IsaFake , LdsChunk , LSQ< Impl > , LSQUnit< Impl > , MaltaCChip , MaltaIO , MmDisk , MuxingKvmGic , NoMaliGpu , NSGigE , PciVirtIO , PerfKvmCounter , PioDevice , PipeFDEntry , Pl011 , PL031 , Pl050 , Pl111 , Pl390 , PortProxy , ProtoInputStream , RawDiskImage , RealViewCtrl::Device , RealViewCtrl , RealViewOsc , RealViewTemperatureSensor , SatCounter , SimpleDisk , Sinic::Device , Sinic::Regs::Info , Sp804 , Sp804::Timer , Terminal , Trace::NativeTrace , TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream , TsunamiCChip , TsunamiIO , TsunamiPChip , Uart8250 , UFSHostDevice , VecRegisterState , VectorRegisterFile , VGic , VirtDescriptor , VirtIO9PDiod , VirtIO9PProxy , VirtIO9PSocket , VirtIOBlock , VirtQueue::VirtRing< T > , VncServer , X86ISA::Cmos , X86ISA::I8042 , X86ISA::I82094AA , X86ISA::I8237 , X86ISA::I8254 , X86ISA::I8259 , X86ISA::Interrupts , X86ISA::Speaker , X86ISA::Walker::WalkerState
• read1() : VncServer
• read_accesses : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• read_acv : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• read_byte : Intel8254Timer::Counter
• read_hits : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• read_misses : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• readAccess : FlashDevice::FlashDeviceStats
• readAccesses : ArmISA::TLB
• readAddrDist : CommMonitor::MonitorStats
• readAddrMask : CommMonitor::MonitorStats
• readAll() : VirtIO9PProxy
• readArchCCReg() : FullO3CPU< Impl >
• readArchFloatReg() : FullO3CPU< Impl >
• readArchFloatRegInt() : FullO3CPU< Impl >
• readArchIntReg() : FullO3CPU< Impl >
• readBandwidthHist : CommMonitor::MonitorStats
• readBit() : AbstractBloomFilter , BlockBloomFilter , BulkBloomFilter , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter
• readBlob() : FSTranslatingPortProxy , PortProxy , SETranslatingPortProxy
• readBufferSize : DRAMCtrl
• readBurstLengthHist : CommMonitor::MonitorStats
• readBursts : DRAMCtrl
• readByte() : SubBlock
• readBytes : CommMonitor::MonitorStats
• readCallArgMem() : Wavefront
• readCallback() : GPUCoalescer , Sequencer , UFSHostDevice , UFSHostDevice::UFSSCSIDevice
• readCCReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , O3ThreadContext< class > , PhysRegFile , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readCCRegFlat() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readCCRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• ReadCleanReq : MemCmd
• readCommand() : IdeDisk
• readComplete() : DRAMSim2
• readCompleted : UFSHostDevice::UFSSCSIDevice
• readCompleteEvent : CopyEngine::CopyEngineChannel
• readCompressedTrace() : RubySystem
• readConfig() : IdeController , PciDevice , VirtIO9PBase , VirtIOBlock , VirtIOConsole , VirtIODeviceBase
• readConfigBlob() : VirtIODeviceBase
• readControl() : IdeDisk
• ReadControllerRamBase : X86ISA::I8042
• readCopyBytes() : CopyEngine::CopyEngineChannel
• readCopyBytesComplete() : CopyEngine::CopyEngineChannel
• readCounter() : Intel8254Timer , X86ISA::I8254
• readCpu() : BaseGicRegisters , KvmKernelGicV2 , Pl390
• readCtrl() : VGic
• readData() : MC146818
• ReadData : X86ISA::PS2Mouse
• readDataOut() : X86ISA::I8042
• readDataTimed() : ArmISA::Stage2MMU
• readDataUntimed() : ArmISA::Stage2MMU
• readDevice() : UFSHostDevice
• readDisk() : IdeDisk
• readDistributor() : BaseGicRegisters , KvmKernelGicV2 , Pl390
• readDone() : UFSHostDevice
• readDoneEvent : UFSHostDevice
• readEnergy : DRAMCtrl::Rank
• readEntries : DRAMCtrl::Rank
• readEvent : Pl111
• ReadExReq : MemCmd
• ReadExResp : MemCmd
• readFillStart() : SparcProcess
• readFlash() : UFSHostDevice::UFSSCSIDevice
• readFloatReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , O3ThreadContext< class > , PhysRegFile , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readFloatRegBits() : CheckerThreadContext< TC > , FullO3CPU< Impl > , O3ThreadContext< class > , PhysRegFile , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readFloatRegBitsFlat() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readFloatRegFlat() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readFloatRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readFloatRegOperandBits() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readFramebuffer() : Pl111
• readFreeEntries() : DefaultRename< Impl >
• readFSReg() : SparcISA::ISA
• readFuncExeInst() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• readGarbage() : UFSHostDevice
• readGarbageEventQueue : UFSHostDevice
• readHeader() : VirtQueue::VirtRing< T >
• readHeadInst() : ROB< Impl >
• readHits : ArmISA::TLB
• readId() : AmbaDevice
• ReadID : X86ISA::PS2Keyboard , X86ISA::PS2Mouse
• ReadInputPort : X86ISA::I8042
• readIntReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , O3ThreadContext< class > , PhysRegFile , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readIntRegFlat() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• readIntRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readIob() : Iob
• readIpr() : AlphaISA::ISA
• readIRR : X86ISA::I8259
• readJBus() : Iob
• readLastActivate() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• readLastSuspend() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• readLatency : FlashDevice::FlashDeviceStats , FlashDevice
• readLatencyHist : CommMonitor::MonitorStats
• readLinearHist : StackDistProbe
• readLogHist : StackDistProbe
• readMem() : AtomicSimpleCPU , BaseSimpleCPU , CheckerCPU , ExecContext
• ReadMem() : Shader
• readMem() : SimpleExecContext , TimingSimpleCPU
• readMemory() : AbstractNVM , FlashDevice
• readMiscReg() : AlphaISA::ISA , ArmISA::BaseISADevice , ArmISA::DummyISADevice , ArmISA::ISA , ArmISA::PMU , BaseO3DynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , ExecContext , FullO3CPU< Impl > , GenericTimer , GenericTimerISA , GPUExecContext , HsailISA::GPUISA , Minor::ExecContext , MipsISA::ISA , O3ThreadContext< class > , PowerISA::ISA , ProxyThreadContext< TC > , RiscvISA::ISA , SimpleExecContext , SimpleThread , SparcISA::ISA , ThreadContext , X86ISA::ISA
• readMiscRegInt() : ArmISA::PMU
• readMiscRegNoEffect() : AlphaISA::ISA , ArmISA::ISA , CheckerCPU , CheckerThreadContext< TC > , FullO3CPU< Impl > , Minor::ExecContext , MipsISA::ISA , O3ThreadContext< class > , PowerISA::ISA , ProxyThreadContext< TC > , RiscvISA::ISA , SimpleThread , SparcISA::ISA , ThreadContext , X86ISA::ISA
• readMiscRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readMisses : ArmISA::TLB
• readNextWindow() : TraceCPU::ElasticDataGen
• readObservations : MemChecker::ByteTracker
• READONLY : HsaCode
• ReadOnly : PageTableBase
• readonly : RawDiskImage
• readonly_data : HsaCode
• READONLY_SEGMENT : Request
• readonly_size : HsaDriverSizes , HsailCode
• readonlyData : HsaObject
• ReadOutputPort : X86ISA::I8042
• readPC() : ArmISA::ArmStaticInst
• readPendingNum : UFSHostDevice
• readPercent : LinearGen , RandomGen
• readPktSize : DRAMCtrl
• readPorts : RubyTester
• readPredicate() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , ProxyThreadContext< TC > , SimpleExecContext , SimpleThread
• readPredTaken() : BaseDynInst< Impl >
• readPredTarg() : BaseDynInst< Impl >
• readQueue : DRAMCtrl
• readQueueFull() : DRAMCtrl
• readReg() : HDLcd , NoMaliGpu , X86ISA::I82094AA , X86ISA::Interrupts
• readRegister() : X86ISA::Cmos
• readRegOtherThread() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext , ThreadContext
• readRegRaw() : NoMaliGpu
• ReadReq : MemCmd
• readReqs : DRAMCtrl
• ReadResp : MemCmd
• ReadRespWithInvalidate : MemCmd
• readResult() : BaseDynInst< Impl >
• readRowHitRate : DRAMCtrl
• readRowHits : DRAMCtrl
• ReadSharedReq : MemCmd
• readSpillStart() : SparcProcess
• readsSCC() : GPUDynInst , GPUStaticInst
• readStallSignals() : DefaultDecode< Impl > , DefaultRename< Impl >
• readStCondFailures() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , ExecContext , Minor::ExecContext , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleExecContext , SimpleThread , ThreadContext
• readsThisTime : DRAMCtrl
• readString() : SETranslatingPortProxy , X86ISA::SMBios::SMBiosStructure
• readsVCC() : GPUDynInst , GPUStaticInst
• readTailInst() : ROB< Impl >
• ReadTestInputs : X86ISA::I8042
• readTrans : CommMonitor::MonitorStats
• readTransHist : CommMonitor::MonitorStats
• readVCpu() : VGic
• readWord() : PixelConverter
• ReadWriteVal : Intel8254Timer
• ready() : Wavefront
• Ready : X86ISA::Walker::WalkerState
• ReadyInstQueue : InstructionQueue< Impl >
• readyInsts : InstructionQueue< Impl >
• readyIt : InstructionQueue< Impl >
• readyIter : MSHR , WriteQueueEntry
• readyList : ComputeUnit , Queue< Entry > , ScoreboardCheckStage , TraceCPU::ElasticDataGen
• readyRegs : BaseDynInst< Impl >
• readyTime : DRAMCtrl::DRAMPacket , MSHR::Target , QueueEntry , WriteQueueEntry::Target
• readyToCkpt() : DistIface
• readyToCommit() : BaseDynInst< Impl >
• readyToExit() : DistIface
• readyToIssue() : BaseDynInst< Impl >
• ReadyWorkgroup() : ComputeUnit
• real : SparcISA::TlbRange
• RealView() : RealView
• RealViewCtrl() : RealViewCtrl
• RealViewOsc() : RealViewOsc
• RealViewTemperatureSensor() : RealViewTemperatureSensor
• reanalyzeAllMessages() : MessageBuffer
• reanalyzeList() : MessageBuffer
• reanalyzeMessages() : MessageBuffer
• reason : Minor::BranchData
• Reason : Minor::BranchData
• receiveDeviceInterrupt() : Iob
• receiveJBusInterrupt() : Iob
• receiver : BasicSignal
• RECEIVING_ADDR : I2CBus
• RECEIVING_DATA : I2CBus
• recent : DecodeCache::AddrMap< Value >
• reconvergenceStack : Wavefront
• Record : ElasticTrace , TraceCPU::ElasticDataGen
• record_t : PCEventQueue
• recordCacheContents() : CacheMemory
• recordCacheTrace() : AbstractController
• recordCPReadCallBack() : GPUCoalescer
• recordCPWriteCallBack() : GPUCoalescer
• recordExecTick() : ElasticTrace
• recordIndirect() : IndirectPredictor
• recordMissLatency() : GPUCoalescer , Sequencer
• recordPCChange() : CheckerCPU
• recordProducer() : InstructionQueue< Impl >
• recordRequestType() : CacheMemory , DirectoryMemory , DMASequencer , GPUCoalescer , Sequencer
• recordResult() : BaseDynInst< Impl >
• RecordResult : BaseDynInst< Impl >
• recordTarget() : IndirectPredictor
• recordToCommTick() : ElasticTrace
• RecordType : ElasticTrace , TraceCPU::ElasticDataGen
• RecoverInst : BaseDynInst< Impl >
• recoveryPage : UFSHostDevice::UFSSCSIDevice
• recreateable() : OutputFile< StreamType > , OutputStream
• recv() : BaseRemoteGDB
• recvAtomic() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , Cache::CpuSidePort , Cache , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , GpuDispatcher::TLBPort , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , MessageSlavePort , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , PioPort , RubyPort::MemSlavePort , RubyPort::PioSlavePort , SerialLink::SerialLinkSlavePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvAtomicSnoop() : AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUDPort , Cache::MemSidePort , Cache , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , TrafficGen::TrafficGenPort
• recvCommand() : CopyEngine::CopyEngineChannel
• recvCutText() : VncServer
• recvDone : DistIface::RecvScheduler , EtherInt
• recvFunctional() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , Cache::CpuSidePort , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , GpuDispatcher::TLBPort , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , RubyPort::MemSlavePort , RubyPort::PioSlavePort , SerialLink::SerialLinkSlavePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvFunctionalSnoop() : AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUDPort , Cache::MemSidePort , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , FullO3CPU< Impl >::DcachePort , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , Minor::LSQ::DcachePort , StubSlavePort , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort , TrafficGen::TrafficGenPort
• recvHeader() : DistIface , TCPIface
• recvKeyboardInput() : VncServer
• recvMessage() : MessageSlavePort , X86ISA::IntDevice::IntSlavePort , X86ISA::IntDevice , X86ISA::Interrupts
• recvPacket() : DistEtherLink::LocalIface , DistIface , EtherInt , EtherLink::Interface , EtherSwitch::Interface , EtherTapInt , IGbEInt , NSGigE , NSGigEInt , Sinic::Device , Sinic::Interface , TCPIface , X86ISA::Walker::WalkerState
• recvPointerInput() : VncServer
• recvRangeChange() : AddrMapper::MapperMasterPort , AddrMapper , BaseXBar , CoherentXBar::CoherentXBarMasterPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , GpuDispatcher::TLBPort , HMCController , LdsState::CuSidePort , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , NoncoherentXBar::NoncoherentXBarMasterPort , RubyPort::MemMasterPort , RubyPort::PioMasterPort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvReal() : EtherTapBase , EtherTapStub
• recvReqRetry() : AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUPort , BaseKvmCPU::KVMCpuPort , Bridge::BridgeMasterPort , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CoherentXBar::SnoopRespPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DefaultFetch< Impl > , DmaPort , FullO3CPU< Impl >::DcachePort , FullO3CPU< Impl >::IcachePort , GarnetSyntheticTraffic::CpuPort , GpuDispatcher::TLBPort , LSQ< Impl > , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , Minor::Fetch1::IcachePort , Minor::Fetch1 , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentXBar::NoncoherentXBarMasterPort , NoncoherentXBar , QueuedMasterPort , RubyDirectedTester::CpuPort , RubyTester::CpuPort , SerialLink::SerialLinkMasterPort , System::SystemPort , TimingSimpleCPU::DcachePort , TimingSimpleCPU::IcachePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , TraceCPU::DcachePort , TraceCPU::IcachePort , TrafficGen , TrafficGen::TrafficGenPort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::Walker , X86ISA::Walker::WalkerPort
• recvResponse() : MessageMasterPort , X86ISA::I82094AA , X86ISA::IntDevice::IntMasterPort , X86ISA::IntDevice , X86ISA::Interrupts
• recvRespRetry() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , CommMonitor::MonitorSlavePort , CommMonitor , DRAMSim2::MemoryPort , DRAMSim2 , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , QueuedSlavePort , SerialLink::SerialLinkSlavePort , SimpleMemory::MemoryPort , SimpleMemory , SlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort
• recvRetry() : BaseXBar::Layer< SrcType, DstType > , LdsState::CuSidePort , LSQUnit< Impl > , MemTest
• recvRetrySnoopResp() : CommMonitor::MonitorMasterPort , CommMonitor , MasterPort , QueuedMasterPort
• recvScheduler : DistIface
• RecvScheduler() : DistIface::RecvScheduler
• recvSimulated() : EtherTapBase
• recvTCP() : TCPIface
• recvThread : DistIface
• recvThreadFunc() : DistIface
• recvThreadsNum : DistIface
• recvTick : EtherSwitch::Interface::PortFifoEntry
• recvTime : MSHR::Target , WriteQueueEntry::Target
• recvTimingReq() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , Cache::CpuSidePort , Cache , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , HMCController , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , RubyPort::MemSlavePort , RubyPort::PioSlavePort , SerialLink::SerialLinkSlavePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , X86ISA::GpuTLB::CpuSidePort
• recvTimingResp() : AbstractController::MemoryPort , AbstractController , AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUPort , BaseKvmCPU::KVMCpuPort , Bridge::BridgeMasterPort , Cache::MemSidePort , Cache , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CoherentXBar::SnoopRespPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DmaPort , FullO3CPU< Impl >::DcachePort , FullO3CPU< Impl >::IcachePort , GarnetSyntheticTraffic::CpuPort , GpuDispatcher::TLBPort , LSQ< Impl > , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , MessageMasterPort , Minor::Fetch1::IcachePort , Minor::Fetch1 , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentXBar::NoncoherentXBarMasterPort , NoncoherentXBar , RubyDirectedTester::CpuPort , RubyPort::MemMasterPort , RubyPort::PioMasterPort , RubyPort , RubyTester::CpuPort , SerialLink::SerialLinkMasterPort , System::SystemPort , TimingSimpleCPU::DcachePort , TimingSimpleCPU::IcachePort , TLBCoalescer::MemSidePort , TraceCPU::DcachePort , TraceCPU::IcachePort , TrafficGen::TrafficGenPort , X86ISA::GpuTLB::MemSidePort , X86ISA::Walker , X86ISA::Walker::WalkerPort
• recvTimingSnoopReq() : AddrMapper::MapperMasterPort , AddrMapper , Cache::MemSidePort , Cache , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , FullO3CPU< Impl >::DcachePort , LSQ< Impl > , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , Minor::LSQ::DcachePort , Minor::LSQ , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort , TraceCPU::IcachePort , TrafficGen::TrafficGenPort
• recvTimingSnoopResp() : AddrMapper::MapperSlavePort , AddrMapper , Cache::CpuSidePort , Cache , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , SlavePort , StubSlavePort
• recvTMsg() : VirtIO9PBase , VirtIO9PProxy
• recycle() : MessageBuffer , WireBuffer
• red : Bitmap::BmpPixel32 , Pixel
• Red_Select : HDLcd
• red_select : HDLcd
• redirTable : X86ISA::I82094AA
• redmax : VncInput::PixelFormat
• redshift : VncInput::PixelFormat
• ReExec() : ReExec
• ref : Brig::BrigOperandCodeRef
• REF_DRAIN : DRAMCtrl
• REF_IDLE : DRAMCtrl
• REF_PD_EXIT : DRAMCtrl
• REF_PRE : DRAMCtrl
• REF_RUN : DRAMCtrl
• REF_SREF_EXIT : DRAMCtrl
• REF_START : DRAMCtrl
• refcount : BaseRemoteGDB::HardBreakpoint
• refCount : CacheBlk
• RefCounted() : RefCounted
• refCounter : LdsState
• RefCountingPtr() : RefCountingPtr< T >
• referenced : IniFile::Entry , IniFile::Section
• referenceData : MemTest
• references : ThermalModel
• refLabel() : HsailCode , LabelMap
• refresh() : PerfKvmCounter , VPtr< T >
• refreshDueAt : DRAMCtrl::Rank
• refreshEnergy : DRAMCtrl::Rank
• refreshEvent : DRAMCtrl::Rank
• refreshNext : CopyEngine::CopyEngineChannel
• refreshState : DRAMCtrl::Rank
• RefreshState : DRAMCtrl
• reg : Brig::BrigOperandAddress
• Reg() : CopyEngineReg::Reg< T >
• reg() : EtherBus
• Reg() : iGbReg::Regs::Reg< T >
• reg : RegAddrOperand< RegOperandType > , TimingExprReadIntReg , X86ISA::EmulEnv
• reg0 : ArmISA::Mult3
• reg1 : ArmISA::Mult3
• reg2 : ArmISA::Mult3
• reg3 : ArmISA::Mult4
• reg_frame : pdr
• reg_op : RegOrImmOperand< RegOperand, T >
• reg_pmceid : ArmISA::PMU
• reg_pmcnten : ArmISA::PMU
• reg_pmcr : ArmISA::PMU
• reg_pmcr_conf : ArmISA::PMU
• reg_pmcr_wr_mask : ArmISA::PMU
• reg_pminten : ArmISA::PMU
• reg_pmovsr : ArmISA::PMU
• reg_pmselr : ArmISA::PMU
• regBusy() : ConditionRegisterState , VectorRegisterFile
• regCache : MipsISA::RemoteGDB , PowerISA::RemoteGDB , RiscvISA::RemoteGDB
• regCache32 : ArmISA::RemoteGDB , SparcISA::RemoteGDB , X86ISA::RemoteGDB
• regCache64 : ArmISA::RemoteGDB , SparcISA::RemoteGDB , X86ISA::RemoteGDB
• regCachePtr : BaseRemoteGDB
• regControllerCapabilities : UFSHostDevice
• regControllerDEVID : UFSHostDevice
• regControllerEnable : UFSHostDevice
• regControllerPRODID : UFSHostDevice
• regControllerStatus : UFSHostDevice
• regData32() : Sinic::Device
• regData64() : Sinic::Device
• regData8() : Sinic::Device
• regDataAvailCallback() : Terminal
• regDep : TraceCPU::ElasticDataGen::GraphNode
• RegDepArray : TraceCPU::ElasticDataGen::GraphNode
• regenerateBlkAddr() : BaseSetAssoc , BaseTags , FALRU
• regEtraceListeners() : ElasticTrace
• regEtraceListenersEvent : ElasticTrace
• regFile : FullO3CPU< Impl > , UnifiedFreeList , UnifiedRenameMap
• regFileChar : BaseRegOperand
• regIdx : BaseRegOperand
• regIdxVec : ComputeUnit
• RegImmImmOp() : RegImmImmOp
• RegImmOp() : RegImmOp
• RegImmRegOp() : RegImmRegOp
• RegImmRegShiftOp() : RegImmRegShiftOp
• RegIndex : BaseDynInst< Impl > , BaseO3DynInst< Impl >
• regIndex() : BaseOperand , BaseRegOperand
• RegIndex : DefaultRename< Impl > , Minor::Scoreboard
• regIndex() : RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• RegIndex : ROB< Impl > , SimpleRenameMap , StaticInst , UnifiedRenameMap
• RegIndexVector : ArmKvmCPU , BaseArmKvmCPU
• regInterruptEnable : UFSHostDevice
• regInterruptStatus : UFSHostDevice
• regionSize() : PoolManager , SimplePoolManager
• registerAbstractController() : RubySystem
• registerCU() : Shader
• registerDequeueCallback() : MessageBuffer
• registerDevice() : PciHost , RealViewCtrl
• registerDrainable() : DrainManager
• registered : EmbeddedPyBind
• registerEvent() : ComputeUnit
• registerHandler() : ExternalMaster , ExternalSlave
• registerKickCallback() : VirtIODeviceBase
• registerNetwork() : RubySystem
• RegisterOffset : HDLcd
• registerPowerProducer() : SubSystem
• registerQueue() : VirtIODeviceBase
• Registers : EnergyCtrl
• registerSrcClockDom() : VoltageDomain
• registerThreadContext() : System
• registerType : BaseOperand
• registerWithClockDomain() : ClockDomain
• regKind : Brig::BrigOperandRegister , BrigRegOperandInfo
• regm : X86ISA::EmulEnv
• regmask : pdr
• RegMiscRegImmOp() : RegMiscRegImmOp
• regMode : ArmISA::SrsOp
• regNum : Brig::BrigOperandRegister
• regNxtBusy() : VectorRegisterFile
• regoffset : pdr
• RegOp() : X86ISA::RegOp
• RegOpBase() : X86ISA::RegOpBase
• regOperandSize : BaseOperand
• RegOpImm() : X86ISA::RegOpImm
• RegOrImmOperand() : RegOrImmOperand< RegOperand, T >
• regProbeListeners() : BaseMemProbe , ElasticTrace , SimObject , SimpleTrace , SimPoint
• regProbePoints() : ArmISA::TLB , AtomicSimpleCPU , BPredUnit , CommMonitor , DefaultCommit< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , PowerModel , SimObject
• RegRegImmImmOp() : RegRegImmImmOp
• RegRegImmImmOp64() : RegRegImmImmOp64
• RegRegImmOp() : RegRegImmOp
• RegRegOp() : RegRegOp
• RegRegRegImmOp() : RegRegRegImmOp
• RegRegRegImmOp64() : RegRegRegImmOp64
• RegRegRegOp() : RegRegRegOp
• RegRegRegRegOp() : RegRegRegRegOp
• regs : CopyEngine , IGbE , NSGigE , Sinic::Device , X86ISA::Cmos , X86ISA::Interrupts
• regScoreboard : InstructionQueue< Impl >
• regScoreBoard : Scoreboard
• regSel : X86ISA::I82094AA
• regSize() : VecRegisterState
• RegsPerWindow : SparcISA::ISA
• regsReady : MemDepUnit< MemDepPred, Impl >::MemDepEntry , MemDepUnit< MemDepPred, Impl >
• regsReset() : NSGigE
• regStats() : AbstractController , AbstractMemory , AddressProfiler , AlphaISA::Kernel::Statistics , AlphaISA::TLB , ArmISA::TableWalker , ArmISA::TLB , BaseCache , BaseKvmCPU , BaseO3CPU , BasePrefetcher , BaseSimpleCPU , BaseTags , BaseXBar::Layer< SrcType, DstType > , BaseXBar , BPredUnit , Cache , CacheMemory , CheckerThreadContext< TC > , ClockDomain , ClockedObject , CoherentXBar , CommMonitor , ComputeUnit , ConditionRegisterState , CopyEngine , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DRAMCtrl::Rank , DRAMCtrl , ElasticTrace , EtherDevice , ExecStage , FALRU , FetchStage , FlashDevice , FullO3CPU< Impl > , GarnetNetwork , GlobalMemPipeline , GPUCoalescer , HDLcd , IdeDisk , InstructionQueue< Impl > , Kernel::Statistics , LocalMemPipeline , LSQ< Impl > , LSQUnit< Impl > , MathExprPowerModel , MemDepUnit< MemDepPred, Impl > , MemFootprintProbe , MemTest , MessageBuffer , Minor::MinorStats , MinorCPU , MipsISA::TLB , NoncoherentXBar , O3ThreadContext< class > , PowerISA::TLB , PowerModel , PowerModelState , Prefetcher , Process , Profiler , ProxyThreadContext< TC > , QueuedPrefetcher , RiscvISA::TLB , ROB< Impl > , Router , RubySystem , ScheduleStage , ScoreboardCheckStage , Sequencer , SimObject , SimpleNetwork , SimpleThread , Sinic::Device , SnoopFilter , StackDistProbe , Switch , System , ThermalDomain , ThreadContext , Throttle , Ticked , TickedObject , TLBCoalescer , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TraceCPU , TrafficGen , UFSHostDevice , VecRegisterState , VoltageDomain , Wavefront , X86ISA::GpuTLB
• regUFSVersion : UFSHostDevice
• regUICCommand : UFSHostDevice
• regUICCommandArg1 : UFSHostDevice
• regUICCommandArg2 : UFSHostDevice
• regUICCommandArg3 : UFSHostDevice
• regUICErrorCodeDataLinkLayer : UFSHostDevice
• regUICErrorCodeDME : UFSHostDevice
• regUICErrorCodeNetworkLayer : UFSHostDevice
• regUICErrorCodePHYAdapterLayer : UFSHostDevice
• regUICErrorCodeTransportLayer : UFSHostDevice
• regUTPTaskREQDoorbell : UFSHostDevice
• regUTPTaskREQListBaseH : UFSHostDevice
• regUTPTaskREQListBaseL : UFSHostDevice
• regUTPTaskREQListClear : UFSHostDevice
• regUTPTaskREQListRunStop : UFSHostDevice
• regUTPTransferREQDoorbell : UFSHostDevice
• regUTPTransferREQINTAGGControl : UFSHostDevice
• regUTPTransferREQListBaseH : UFSHostDevice
• regUTPTransferREQListBaseL : UFSHostDevice
• regUTPTransferREQListClear : UFSHostDevice
• regUTPTransferREQListRunStop : UFSHostDevice
• regVal : X86ISA::ISA
• relativeTick : BasePixelPump::PixelEvent
• release() : Event , Linux::utsname , OperatingSystem::utsname
• RELEASE : Request
• release() : SimpleMemory , Solaris::utsname , TraceCPU::ElasticDataGen::HardwareResource
• releaseDate : X86ISA::SMBios::BiosInformation
• releaseEvent : BaseXBar::Layer< SrcType, DstType > , SimpleMemory
• releaseImpl() : Event , PyEvent
• releaseLayer() : BaseXBar::Layer< SrcType, DstType >
• releaseSpace() : LdsState
• releaseStoreBuffer() : TraceCPU::ElasticDataGen::HardwareResource
• reloadRegMap() : SparcISA::ISA
• relocatable() : ElfObject , ObjectFile
• relocate : ElfObject , OutputFile< StreamType > , OutputStream
• remainingSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• remap() : FlashDevice , FuncPageTable , MultiLevelPageTable< ISAOps > , PageTableBase , Wavefront
• remapAddr() : AddrMapper , RangeAddrMapper
• remappedRanges : RangeAddrMapper
• RemoteGDB() : AlphaISA::RemoteGDB , ArmISA::RemoteGDB , MipsISA::RemoteGDB , PowerISA::RemoteGDB , RiscvISA::RemoteGDB , SparcISA::RemoteGDB
• remoteGDB : System
• RemoteGDB() : X86ISA::RemoteGDB
• remoteIRR : X86ISA::I82094AA , X86ISA::Interrupts
• RemoteMode : X86ISA::PS2Mouse
• remove : BreakPCEvent , DependencyGraph< DynInstPtr > , EventQueue , NetDest , OutputDirectory , PacketFifo , PCEvent , PCEventQueue , PollQueue , Set , Trie< Key, Value >
• removeDepOnInst() : TraceCPU::ElasticDataGen::GraphNode
• removeEntries() : LSQ< Impl >
• removeFromHistory() : DefaultRename< Impl >
• removeFrontInst() : FullO3CPU< Impl >
• removeHardBreak() : BaseRemoteGDB
• removeInLSQ() : BaseDynInst< Impl >
• removeInstsNotInROB() : FullO3CPU< Impl >
• removeInstsThisCycle : FullO3CPU< Impl >
• removeInstsUntil() : FullO3CPU< Impl >
• removeItem() : Event
• removeList : FullO3CPU< Impl >
• removeListener() : ProbeManager , ProbePoint , ProbePointArg< T >
• removeNetDest() : NetDest
• removeRegDep() : TraceCPU::ElasticDataGen::GraphNode
• removeRegDepMapEntry() : ElasticTrace
• removeRequest() : GPUCoalescer
• removeRobDep() : TraceCPU::ElasticDataGen::GraphNode
• removeSet() : Set
• removeSoftBreak() : BaseRemoteGDB
• removeThread() : FullO3CPU< Impl >
• rename() : CxxConfigManager , DefaultDecode< Impl >::Stalls , DefaultRename< Impl > , FullO3CPU< Impl >
• Rename : SimpleCPUPolicy< Impl >
• rename() : SimpleRenameMap , UnifiedRenameMap
• renameBlock : TimeBufStruct< Impl >
• renameBlockCycles : DefaultRename< Impl >
• renameCC() : UnifiedRenameMap
• renameCommittedMaps : DefaultRename< Impl >
• renamedDestRegIdx() : BaseDynInst< Impl >
• renameDestReg() : BaseDynInst< Impl >
• renameDestRegs() : DefaultRename< Impl >
• renamedSerializing : DefaultRename< Impl >
• renamedSrcRegIdx() : BaseDynInst< Impl >
• renamedTempSerializing : DefaultRename< Impl >
• renameFloat() : UnifiedRenameMap
• renameFullRegistersEvents : DefaultRename< Impl >
• RenameHistory() : DefaultRename< Impl >::RenameHistory
• renameIdleCycles : DefaultRename< Impl >
• RenameIdx : FullO3CPU< Impl >
• RenameInfo : SimpleRenameMap
• renameInfo : TimeBufStruct< Impl >
• RenameInfo : UnifiedRenameMap
• renameInsts() : DefaultRename< Impl >
• renameInt() : UnifiedRenameMap
• renameIQFullEvents : DefaultRename< Impl >
• renameLQFullEvents : DefaultRename< Impl >
• RenameMap : DefaultCommit< Impl >
• renameMap : DefaultCommit< Impl >
• RenameMap : DefaultIEW< Impl > , DefaultRename< Impl >
• renameMap : DefaultRename< Impl > , FullO3CPU< Impl >
• RenameMap : SimpleCPUPolicy< Impl >
• renameMisc() : UnifiedRenameMap
• renameQueue : DefaultCommit< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• renameRenamedInsts : DefaultRename< Impl >
• renameRenamedOperands : DefaultRename< Impl >
• renameRenameLookups : DefaultRename< Impl >
• renameROBFullEvents : DefaultRename< Impl >
• renameRunCycles : DefaultRename< Impl >
• renameSerializeStallCycles : DefaultRename< Impl >
• renameSkidInsts : DefaultRename< Impl >
• renameSQFullEvents : DefaultRename< Impl >
• renameSquashCycles : DefaultRename< Impl >
• renameSquashedInsts : DefaultRename< Impl >
• renameSrcReg() : BaseDynInst< Impl >
• renameSrcRegs() : DefaultRename< Impl >
• RenameStatus : DefaultRename< Impl >
• renameStatus : DefaultRename< Impl >
• RenameStruct : DefaultCommit< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , SimpleCPUPolicy< Impl >
• renameToDecodeDelay : DefaultDecode< Impl >
• renameToFetchDelay : DefaultFetch< Impl >
• renameToIEWDelay : DefaultIEW< Impl >
• renameToROBDelay : DefaultCommit< Impl >
• renameUnblock : TimeBufStruct< Impl >
• renameUnblockCycles : DefaultRename< Impl >
• renameUndoneMaps : DefaultRename< Impl >
• renameWidth : DefaultCommit< Impl > , DefaultRename< Impl >
• Renaming() : CxxConfigManager::Renaming
• renamings : CxxConfigManager
• renderFrame() : BasePixelPump
• renderLine() : BasePixelPump
• renderPixels() : BasePixelPump
• reorderQueue() : DRAMCtrl
• repeat : GlobalSimLoopExitEvent , GlobalSyncEvent , LocalSimLoopExitEvent , Stats::StatEvent
• replaceHead() : EventQueue
• replacements : BaseTags
• replaceThreadContext() : BaseRemoteGDB , CpuEvent , System
• replaceUpgrades() : MSHR::TargetList
• replay() : MemDepUnit< MemDepPred, Impl >
• replayMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• replicate : ArmISA::MicroNeonMixLaneOp64 , ArmISA::VldSingleOp64 , ArmISA::VstSingleOp64
• replicatePage() : Process
• reportData() : Minor::BranchData , Minor::Fetch1::FetchRequest , Minor::ForwardInstData , Minor::ForwardLineData , Minor::LSQ::LSQRequest , Minor::MinorDynInst , Minor::QueuedInst , Minor::ReportIF , Minor::ReportTraitsAdaptor< ElemType > , Minor::ReportTraitsPtrAdaptor< PtrType >
• reportLeft : Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits >
• reportRight : Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits >
• req : ArmISA::Stage2LookUp , ArmISA::Stage2MMU::Stage2Translation , ArmISA::TableWalker::WalkerState , DefaultFetch< Impl >::FinishTranslationEvent , LSQUnit< Impl >::SQEntry , Packet , X86ISA::Walker::WalkerState
• req_tick_latency : ComputeUnit
• reqCnt : X86ISA::GpuTLB::TranslationState
• reqCoalescer : GPUCoalescer
• reqFlags : AlphaISA::DtbFault , DmaReadFifo , ElasticTrace::TraceInfo
• reqIPI() : MaltaCChip , TsunamiCChip
• ReqLayer() : BaseXBar::ReqLayer
• reqLayers : CoherentXBar , NoncoherentXBar
• reqLookupResult : SnoopFilter
• ReqMade : BaseDynInst< Impl >
• ReqPacketQueue() : ReqPacketQueue
• reqPos : UFSHostDevice::SCSIResumeInfo , UFSHostDevice::transferDoneInfo
• reqQueue : AbstractController::MemoryPort , MessageMasterPort , QueuedMasterPort , RubyPort::MemMasterPort , RubyPort::PioMasterPort
• reqQueueFull() : Bridge::BridgeMasterPort , SerialLink::SerialLinkMasterPort
• reqQueueLimit : Bridge::BridgeMasterPort , SerialLink::SerialLinkMasterPort
• reqToVerify : BaseDynInst< Impl >
• ReqType : DistHeaderPkt , DistIface
• request : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• Request() : Request
• request_out_datain : UFSHostDevice
• requestCkpt() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• requestCompleted : PrefetchEntry
• RequestDesc() : RequestDesc
• REQUESTED : ArmISA::TableWalker
• requested : SnoopFilter::SnoopItem
• requestExit() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• requestFbUpdate() : VncServer
• requestHandler() : UFSHostDevice
• RequestIn : UFSHostDevice::SCSIResumeInfo
• requestInterrupt() : X86ISA::I8259 , X86ISA::Interrupts
• requestIssued : PrefetchEntry
• RequestIssuing : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• RequestNeedsRetry : Minor::LSQ::LSQRequest
• requestOut : UFSHostDevice::transferDoneInfo
• RequestQueue() : VirtIOBlock::RequestQueue
• requests : Minor::Fetch1 , Minor::LSQ
• requestSize() : DmaReadFifo::DmaDoneEvent
• requestStopSync() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• RequestTable : DMASequencer , GPUCoalescer , Sequencer
• RequestType : VirtIOBlock
• res : Minor::LSQ::LSQRequest , WholeTranslationState
• res1 : Linux::pcb_struct
• res2 : Linux::pcb_struct
• res_error_head : SparcISA::ISA
• res_error_tail : SparcISA::ISA
• reschedule() : BaseGlobalEvent , EventManager , EventQueue , MemDepUnit< MemDepPred, Impl >
• rescheduleMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• Resend : X86ISA::PS2Keyboard , X86ISA::PS2Mouse
• reserve() : BankedArray , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , Minor::Reservable , PacketFifo
• Reserved : ArmISA::TableWalker::L1Descriptor , ArmISA::TlbEntry
• reserved : Brig::BrigDirectiveControl , Brig::BrigDirectiveExecutable , Brig::BrigDirectiveFbarrier , Brig::BrigDirectiveModule , Brig::BrigDirectiveVariable , Brig::BrigInstAddr , Brig::BrigInstAtomic , Brig::BrigInstBr , Brig::BrigInstCmp , Brig::BrigInstImage , Brig::BrigInstLane , Brig::BrigInstMem , Brig::BrigInstMod , Brig::BrigInstQuerySampler , Brig::BrigInstQueue , Brig::BrigInstSeg , Brig::BrigInstSourceType , Brig::BrigModuleHeader , Brig::BrigOperandAlign , Brig::BrigOperandConstantBytes , Brig::BrigOperandConstantImage , Brig::BrigOperandConstantOperandList , Brig::BrigOperandConstantSampler , CpuLocalTimer::Timer , ecoff_extsym , ecoff_fdr , ecoff_sym , FXSave
• Reserved : Iob
• reserved : Net::ip6_opt_routing_type2 , PacketFifo , PCIConfig , pdr , PXCAP , UFSHostDevice::UFSHCDSGEntry , UFSHostDevice::UTPUPIURSP , UFSHostDevice::UTPUPIUTaskReq , VirtIOBlock::BlkRequest , X86ISA::PageFault
• Reserved0 : EventBase
• reserved1 : Bitmap::FileHeader , CopyEngineReg::DmaDesc
• reserved2 : Bitmap::FileHeader , CopyEngineReg::DmaDesc , ecoff_fdr
• reserved_15_12 : HDLcd
• reserved_2_0 : HDLcd
• reserved_30_5 : HDLcd
• reserved_31_1 : HDLcd
• reserved_31_12 : HDLcd
• reserved_31_24 : HDLcd
• reserved_31_5 : HDLcd
• reserved_7_5 : HDLcd
• ReservedGrain : ArmISA::TableWalker
• reservedSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• reservedVectorRegs : Wavefront
• reserveSpace() : LdsState
• reset() : ActivityRecorder , AlphaISA::Decoder , ArmISA::Decoder , DefaultBTB , DependencyGraph< DynInstPtr > , DmaReadFifo::DmaDoneEvent , FunctionProfile , IdeDisk , IGbE::DescCache< T >
• Reset : Iob
• reset() : LocalBP , MemChecker , MipsISA::Decoder , NoMaliGpu , PowerISA::Decoder , ProtoInputStream , ReturnAddrStack , RiscvISA::Decoder , SatCounter , Sinic::Device , SparcISA::Decoder , SparcSystem , Stats::AvgSampleStor , Stats::AvgStor , Stats::DataWrapVec< Derived, InfoProxyType > , Stats::DistBase< Derived, Stor > , Stats::DistProxy< Stat > , Stats::DistStor , Stats::Formula , Stats::HistStor , Stats::Info , Stats::InfoAccess , Stats::InfoProxy< Stat, Base > , Stats::ProxyInfo , Stats::SampleStor , Stats::ScalarBase< Derived, Stor > , Stats::SparseHistBase< Derived, Stor > , Stats::SparseHistStor , Stats::StatEvent , Stats::StatStor , Stats::ValueBase< Derived > , Stats::Vector2dBase< Derived, Stor > , TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream , VirtIODeviceBase , X86ISA::Decoder
• Reset : X86ISA::PS2Keyboard , X86ISA::PS2Mouse
• resetAddr64() : ArmSystem
• resetClock() : Clocked
• ResetCtl : RealViewCtrl
• resetEntries() : DefaultIEW< Impl > , InstructionQueue< Impl > , LSQ< Impl > , ROB< Impl >
• resetEventCounts() : ArmISA::PMU
• resetFlags() : MSHR::TargetList
• resetLastStopped() : Ticked
• resetOffset() : StorageMap , StorageSpace
• resetStage() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultRename< Impl >
• resetState() : InstructionQueue< Impl > , LSQUnit< Impl > , ROB< Impl >
• ResetState : X86ISA::Decoder
• resetStats() : AbstractController , BaseSimpleCPU , GPUCoalescer , InputUnit , Router , RubySystem , Sequencer , SimObject , Sinic::Device , Switch
• resetSymtab : SparcSystem
• ResetWrapMode : X86ISA::PS2Mouse
• residualTransferCount : UFSHostDevice::UTPUPIURSP
• resistors : ThermalModel
• resize() : DependencyGraph< DynInstPtr > , FrameBuffer , Minor::ForwardInstData , NetDest , SubBlock
• resizeEntries() : LSQ< Impl >
• resizeLQ() : LSQUnit< Impl >
• resizeRegFiles() : ComputeUnit , Wavefront
• resizeSQ() : LSQUnit< Impl >
• resolution() : BaseKvmTimer , X86ISA::PS2Mouse
• resolve() : OutputDirectory
• resolveFile() : TrafficGen
• resolveSimObject() : CxxConfigManager::SimObjectResolver , PybindSimObjectResolver , SimObjectResolver
• resp_tick_latency : ComputeUnit
• RespLayer() : BaseXBar::RespLayer
• respLayers : CoherentXBar , NoncoherentXBar
• RESPONDER_HAD_WRITABLE : Packet
• responderHadWritable() : Packet
• respondEvent : DRAMCtrl
• response : MemCmd::CommandInfo
• responseCommand() : MemCmd
• responseEvent : StubSlavePort
• ResponseEvent() : StubSlavePort::ResponseEvent
• responseLatency : BaseCache , BaseXBar
• responseLimit : GarnetSyntheticTraffic
• responsePacket : StubSlavePort
• responseQueue : DRAMSim2
• responseStartAddr : UFSHostDevice::transferDoneInfo
• responseUPIU : UFSHostDevice::UTPTransferCMDDesc
• responseUPIULength : UFSHostDevice::UTPTransferReqDesc
• responseUPIUOffset : UFSHostDevice::UTPTransferReqDesc
• RespPacketQueue() : RespPacketQueue
• respQueue : DRAMCtrl , QueuedSlavePort
• respQueueFull() : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• respQueueLimit : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• restartClock() : IGbE
• restartCounter() : Sp804::Timer
• restartStateMachine() : CopyEngine::CopyEngineChannel
• restartTimerCounter() : CpuLocalTimer::Timer
• restartWatchdogCounter() : CpuLocalTimer::Timer
• restore() : ReturnAddrStack
• restoreFileOffsets() : FDArray
• result : ArmISA::MemoryDImmEx64 , ArmISA::MemoryEx64 , ArmISA::MemoryExDImm , ArmISA::MemoryExImm , CheckerCPU , Stats::AvgStor , Stats::BinaryNode< Op > , Stats::ConstNode< T > , Stats::ConstVectorNode< T > , Stats::Formula , Stats::FormulaInfoProxy< Stat > , Stats::FormulaNode , Stats::FunctorProxy< T > , Stats::MethodProxy< T, V > , Stats::Node , Stats::ScalarBase< Derived, Stor > , Stats::ScalarInfo , Stats::ScalarInfoProxy< Stat > , Stats::ScalarProxy< Stat > , Stats::ScalarProxyNode< Stat > , Stats::ScalarStatNode , Stats::StatStor , Stats::SumNode< Op > , Stats::UnaryNode< Op > , Stats::ValueBase< Derived > , Stats::ValueProxy< T > , Stats::VectorBase< Derived, Stor > , Stats::VectorInfo , Stats::VectorInfoProxy< Stat > , Stats::VectorProxy< Stat > , Stats::VectorStatNode
• resultAvailable : TimingExprEvalContext
• ResultReady : BaseDynInst< Impl >
• results : TimingExprEvalContext
• resume() : BasePixelPump::PixelEvent , DrainManager
• Resume : Iob
• resumeFill() : DmaReadFifo
• resumeFillFunctional() : DmaReadFifo
• resumeFillTiming() : DmaReadFifo
• resumeRecvTicks() : DistIface::RecvScheduler
• resumeSerialize : DefaultRename< Impl >
• resumeUnblocking : DefaultRename< Impl >
• resyncMatch() : PL031
• Ret() : HsailISA::Ret
• retData16 : IsaFake
• retData32 : IsaFake
• retData64 : IsaFake
• retData8 : IsaFake
• retireHead() : ROB< Impl >
• retireResponse() : Minor::LSQ::LSQRequest , Minor::LSQ::SingleDataRequest , Minor::LSQ::SpecialDataRequest , Minor::LSQ::SplitDataRequest
• retransmit() : EtherTapBase
• retries : ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::MemSidePort
• RETRY : BaseXBar::Layer< SrcType, DstType >
• retry() : PacketQueue , SyscallReturn , X86ISA::Walker::WalkerState
• retryFlag : SyscallReturn
• retrying : X86ISA::Walker::WalkerState
• retryItem : SnoopFilter
• retryList : RubyPort
• retryMemInsts : InstructionQueue< Impl >
• retryPkt : DefaultFetch< Impl > , GarnetSyntheticTraffic , LSQUnit< Impl > , MemTest , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TrafficGen
• retryPktTick : TrafficGen
• retryRdReq : DRAMCtrl
• retryReq : Bridge::BridgeSlavePort , DRAMSim2 , SerialLink::SerialLinkSlavePort , SimpleMemory
• retryRequest : Minor::LSQ
• retryResp : DRAMSim2 , LdsState , SimpleMemory
• retryRespEvent : TimingSimpleCPU::TimingCPUPort
• retryStalledReq() : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• retryTicks : TrafficGen
• retryTid : DefaultFetch< Impl >
• retryWaiting() : BaseXBar::Layer< SrcType, DstType >
• retryWrReq : DRAMCtrl
• retsys : PAL
• ReturnAddrStack() : ReturnAddrStack
• returnCycle : Minor::Scoreboard
• returnQueue : LdsState
• returnQueuePush() : LdsState
• returnValue() : SyscallReturn
• rev() : AtagRev
• revision : PCIConfig , X86ISA::ACPI::RSDP , X86ISA::ACPI::SysDescTable
• revokeThreadContext() : Process
• rex : X86ISA::ExtMachInst
• rfcr : dp_regs
• rfctl : iGbReg::Regs
• rfd : DNR , RNDXR
• rfdBase : ecoff_fdr
• rfdr : dp_regs
• RfeOp() : ArmISA::RfeOp
• rgb565_be : PixelConverter
• rgb565_le : PixelConverter
• rgba8888_be : PixelConverter
• rgba8888_le : PixelConverter
• right : TimingExprBin
• rightButton : X86ISA::PS2Mouse
• ring : VirtQueue::VirtRing< T > , vring_avail , vring_used
• ringBuffer : PerfKvmCounter
• ringNumPages : PerfKvmCounter
• rip : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• Riscv : ObjectFile
• RiscvFault() : RiscvISA::RiscvFault
• RiscvLinuxProcess() : RiscvLinuxProcess
• RiscvProcess() : RiscvProcess
• RiscvSystem() : RiscvSystem
• rlim_cur : ArmFreebsd32::rlimit , ArmFreebsd64::rlimit , ArmLinux32::rlimit , ArmLinux64::rlimit , Linux::rlimit , OperatingSystem::rlimit
• rlim_max : ArmFreebsd32::rlimit , ArmFreebsd64::rlimit , ArmLinux32::rlimit , ArmLinux64::rlimit , Linux::rlimit , OperatingSystem::rlimit
• rlim_t : Solaris
• rlimit_resources : ArmFreebsd64 , ArmLinux64
• rlpml : iGbReg::Regs
• rndx : AUXU , OPTR
• rob : DefaultCommit< Impl >
• ROB : DefaultCommit< Impl > , DefaultRename< Impl >
• rob : FullO3CPU< Impl >
• ROB() : ROB< Impl > , SimpleCPUPolicy< Impl >
• roBase : Wavefront
• robDep : TraceCPU::ElasticDataGen::GraphNode
• RobDepArray : TraceCPU::ElasticDataGen::GraphNode
• robDepList : ElasticTrace::TraceInfo
• robEntries : DefaultRename< Impl >::FreeEntries
• RobEntry : BaseDynInst< Impl >
• robInfoFromIEW : DefaultCommit< Impl >
• robNum : TraceCPU::ElasticDataGen::GraphNode
• ROBPolicy : ROB< Impl >
• robPolicy : ROB< Impl >
• robReads : ROB< Impl >
• ROBSquashing : DefaultCommit< Impl > , ROB< Impl >
• robSquashing : TimeBufStruct< Impl >::commitComm
• robStatus : ROB< Impl >
• robWrites : ROB< Impl >
• rom : GPUDynInst , NSGigE
• roMemStart : HsaQueueEntry
• roMemTotal : HsaQueueEntry
• romSize : X86ISA::SMBios::BiosInformation
• root : MathExpr
• Root() : Root
• root() : Root , Stats::Formula
• rootdev() : AtagCore
• roSize : Wavefront
• rotate : ArmISA::PredImmOp
• rotate_counter() : HMCController
• rotated_carry : ArmISA::PredImmOp
• rotated_imm : ArmISA::PredImmOp
• rotateValue() : PowerISA::IntRotateOp
• rotC : ArmISA::DataImmOp
• round : Brig::BrigInstCvt , Brig::BrigInstMod
• roundRobin() : DefaultCommit< Impl >
• RoundRobin : DefaultCommit< Impl >
• roundRobin() : DefaultFetch< Impl >
• RoundRobin : DefaultFetch< Impl >
• roundRobinPriority() : MinorCPU
• route_compute() : Router
• Router() : Router
• routers : FaultModel
• routeTo : BaseXBar
• routeToHyp() : ArmISA::ArmFault , ArmISA::DataAbort , ArmISA::FastInterrupt , ArmISA::Interrupt , ArmISA::PrefetchAbort , ArmISA::SupervisorCall , ArmISA::SystemError , ArmISA::UndefinedInstruction
• routeToMonitor() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , ArmISA::DataAbort , ArmISA::FastInterrupt , ArmISA::Interrupt , ArmISA::PrefetchAbort , ArmISA::SystemError
• RoutingUnit() : RoutingUnit
• row : DRAMCtrl::DRAMPacket
• rowAccesses : DRAMCtrl::Bank
• rowBufferSize : DRAMCtrl
• rows : VirtIOConsole::Config
• rowsPerBank : DRAMCtrl
• rpb_cc : Linux::pcb_struct
• rpb_fen : Linux::pcb_struct
• rpb_ksp : Linux::pcb_struct
• rpb_psn : Linux::pcb_struct
• rpb_ptbr : Linux::pcb_struct
• rpb_unique : Linux::pcb_struct
• rpb_usp : Linux::pcb_struct
• rpc : ReconvergenceStackEntry , Wavefront
• rr_counter : HMCController
• rrNextALUWp : ComputeUnit
• rrNextMemID : ComputeUnit
• RRSchedPolicy : Scheduler
• RRSchedulingPolicy() : RRSchedulingPolicy
• rs : MC146818
• RSDP() : X86ISA::ACPI::RSDP
• rsdp : X86System
• rsdt : X86ISA::ACPI::RSDP
• RSDT() : X86ISA::ACPI::RSDT
• rsi : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• rsp : Trace::X86NativeTrace::ThreadState , X86ISA::RemoteGDB::AMD64GdbRegCache
• rsrpd : iGbReg::Regs
• rss : ecoff_fdr
• rss_hash : iGbReg::RxDesc
• rss_type : iGbReg::RxDesc
• rtc : MaltaIO
• RTC() : MaltaIO::RTC
• rtc : TsunamiIO
• RTC() : TsunamiIO::RTC
• rtc : X86ISA::Cmos
• rtcAddr : TsunamiIO
• RTCEvent() : MC146818::RTCEvent
• RTCTickEvent() : MC146818::RTCTickEvent
• rti : PAL
• rtralt() : Net::IpOpt
• rtType2 : Net::ip6_opt_hdr
• rtType2Addr() : Net::Ip6Opt
• rtType2SegLft() : Net::Ip6Opt
• rtType2Type() : Net::Ip6Opt
• rtTypeExt() : Net::Ip6Hdr
• ru_idrss : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_inblock : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_isrss : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_ixrss : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_majflt : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_maxrss : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_minflt : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_msgrcv : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_msgsnd : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_nivcsw : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_nsignals : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_nswap : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_nvcsw : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_oublock : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_stime : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ru_utime : ArmFreebsd32::rusage , ArmFreebsd64::rusage , ArmLinux32::rusage , ArmLinux64::rusage , Linux::rusage , OperatingSystem::rusage
• ruby_eviction_callback() : RubyPort
• ruby_hit_callback() : RubyPort
• RubyDirectedTester() : RubyDirectedTester
• RubyEvent : RubySystem , RubySystem::RubyEvent
• RubyPort() : RubyPort
• RubyPortProxy() : RubyPortProxy
• RubyRequest() : RubyRequest
• RubyStatsCallback() : RubyStatsCallback
• RubySystem() : RubySystem
• RubyTester() : RubyTester
• run() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch , StatTest
• Running : BaseKvmCPU , BaseSimpleCPU , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• running : Intel8254Timer::Counter
• Running : ROB< Impl >
• running : Ticked
• RunningMMIOPending : BaseKvmCPU
• RunningService : BaseKvmCPU
• RunningServiceCompletion : BaseKvmCPU
• runTimer : BaseKvmCPU
• rvec : Stats::VectorDistInfo , Stats::VectorInfoProxy< Stat >
• rw() : ArmISA::TableWalker::LongDescriptor , Intel8254Timer
• rwTable() : ArmISA::TableWalker::LongDescriptor , ArmISA::TableWalker::WalkerState
• rxActive : Sinic::Device
• rxAdvance : NSGigE
• rxBandwidth : EtherDevice
• rxBeginCopy : Sinic::Device
• rxbuf : Terminal
• rxbusy : Pl050
• rxBusy : Sinic::Device
• rxBusyCount : Sinic::Device
• rxBytes : EtherDevice
• rxcfg : dp_regs
• rxCopy : Sinic::Device
• rxCopyDone : Sinic::Device
• rxcsum : iGbReg::Regs
• RxData : Sinic::Device , Sinic::Device::VirtualReg
• rxdctl : iGbReg::Regs
• rxDelay : NSGigE
• rxDesc32 : NSGigE
• rxDesc64 : NSGigE
• rxDescCache : IGbE
• RxDescCache : IGbE , IGbE::RxDescCache
• rxDescCnt : NSGigE
• rxDescRead : NSGigE
• rxDescRefr : NSGigE
• rxDescWrite : NSGigE
• rxDirtyCount : Sinic::Device
• rxDmaAddr : NSGigE , Sinic::Device
• rxDmaData : NSGigE , Sinic::Device
• rxDmaDone() : Sinic::Device
• rxDmaEvent : Sinic::Device
• rxDmaFree : NSGigE
• rxDmaLen : NSGigE , Sinic::Device
• rxDmaPacket : IGbE
• rxDmaReadDone() : NSGigE
• rxDmaReadEvent : NSGigE
• rxDmaState : NSGigE
• rxDmaWriteDone() : NSGigE
• rxDmaWriteEvent : NSGigE
• rxDone() : DistEtherLink::RxLink
• RxDone : Sinic::Device , Sinic::Device::VirtualReg
• rxDoneData : Sinic::Device::VirtualReg
• rxdp : dp_regs
• rxdp_hi : dp_regs
• rxDump() : NSGigE , Sinic::Device
• rxEmpty : Sinic::Device
• rxEnable : NSGigE , Sinic::Base
• rxFifo : IGbE , NSGigE , Sinic::Device
• rxFifoBlock : NSGigE , Sinic::Device
• RxFifoHigh : Sinic::Device
• RxFifoLow : Sinic::Device
• rxFifoPtr : Sinic::Device
• RxFifoSize : Sinic::Device
• rxFilter() : NSGigE , Sinic::Device
• rxFilterEnable : NSGigE
• rxFragPtr : NSGigE
• rxFragWrite : NSGigE
• rxfull : Pl050
• rxHalt : NSGigE
• rxIdle : NSGigE , Sinic::Device
• rxIndex : Sinic::Device::VirtualReg
• rxint : EtherLink::Link
• rxint_enable : Pl050
• rxIntrEvent : Uart8250
• rxIpChecksums : EtherDevice
• rxKick() : NSGigE , Sinic::Device
• RxKickEvent : NSGigE
• rxKickEvent : NSGigE
• RxKickEvent : Sinic::Device
• RxKickEvent::process : NSGigE , Sinic::Device
• rxKickTick : NSGigE , Sinic::Device
• rxLink : DistEtherLink
• RxLink() : DistEtherLink::RxLink
• rxList : Sinic::Device
• rxLow : Sinic::Device
• rxMappedCount : Sinic::Device
• RxMaxCopy : Sinic::Device
• RxMaxIntr : Sinic::Device
• rxPacket : NSGigE
• rxPacketBufPtr : NSGigE
• rxPacketBytes : Sinic::Device::VirtualReg
• rxPacketOffset : Sinic::Device::VirtualReg
• rxPacketRate : EtherDevice
• rxPackets : EtherDevice
• rxparity : Pl050
• rxPktBytes : NSGigE
• rxQueue : Pl050
• rxReset() : NSGigE
• RxState : NSGigE
• rxState : NSGigE , Sinic::Device
• RxState : Sinic::Device
• rxStateMachine() : IGbE
• RxStatus : Sinic::Device
• rxTcpChecksums : EtherDevice
• rxTick : IGbE
• rxUdpChecksums : EtherDevice
• rxUnique : Sinic::Device , Sinic::Device::VirtualReg
• RxWait : Sinic::Device
• rxWriteDelay : IGbE
• rxXferLen : NSGigE