Here is a list of all class members with links to the classes they belong to:

- b -

• b : m5_twin32_t , m5_twin64_t
• ba : PowerISA::CondLogicOp
• backendLatency : DRAMCtrl
• backingStore : PhysicalMemory
• BackingStoreEntry() : BackingStoreEntry
• BadAddressError : MemCmd
• BadClient() : BaseRemoteGDB::BadClient
• bAdd : MathExpr
• BadDevice() : BadDevice
• baddr_t : SimpleDisk
• BadlyPredictedBranch : Minor::BranchData
• BadlyPredictedBranchTarget : Minor::BranchData
• badvaddr : MipsISA::RemoteGDB::MipsGdbRegCache
• bandwidth : SimpleMemory
• Bank() : DRAMCtrl::Bank
• bank : DRAMCtrl::Bank , DRAMCtrl::Command , DRAMCtrl::DRAMPacket
• bankBits : BankedArray , DramGen
• bankConflictPenalty : LdsState
• BankedArray() : BankedArray
• bankedRegs : Pl390
• BankedRegs() : Pl390::BankedRegs
• bankgr : DRAMCtrl::Bank
• bankGroupArch : DRAMCtrl
• bankGroupsPerRank : DRAMCtrl
• bankId : DRAMCtrl::DRAMPacket
• bankRef : DRAMCtrl::DRAMPacket
• banks : BankedArray , DRAMCtrl::Rank , LdsState
• banksPerRank : DRAMCtrl
• BankType : MipsISA::ISA
• bankType : MipsISA::ISA
• BAR0_SIZE_BASE : PciVirtIO
• BARAddrs : PciDevice
• barCnt : Wavefront
• BareIronMipsSystem() : BareIronMipsSystem
• Barrier() : Barrier
• barrier : BaseGlobalEvent
• Barrier() : HsailISA::Barrier
• barrier_id : ComputeUnit
• barrierCnt : Wavefront
• BarrierDataRequest() : Minor::LSQ::BarrierDataRequest
• barrierEvent : BaseGlobalEvent
• BarrierEvent() : BaseGlobalEvent::BarrierEvent , GlobalEvent::BarrierEvent , GlobalSyncEvent::BarrierEvent
• barrierId : Wavefront
• barrierSlots : Wavefront
• BARSize : PciDevice
• base : ArmFreebsdProcessBits::SyscallTable , ArmISA::Memory64 , ArmISA::Memory , ArmISA::RfeOp , ArmISA::Swap , ArmISA::SysDC64 , ArmLinuxProcessBits::SyscallTable , Brig::BrigDirectiveArgBlockEnd , Brig::BrigDirectiveArgBlockStart , Brig::BrigDirectiveComment , Brig::BrigDirectiveControl , Brig::BrigDirectiveExecutable , Brig::BrigDirectiveExtension , Brig::BrigDirectiveFbarrier , Brig::BrigDirectiveLabel , Brig::BrigDirectiveLoc , Brig::BrigDirectiveModule , Brig::BrigDirectiveNone , Brig::BrigDirectivePragma , Brig::BrigDirectiveVariable , Brig::BrigInstAddr , Brig::BrigInstAtomic , Brig::BrigInstBase , Brig::BrigInstBasic , Brig::BrigInstBr , Brig::BrigInstCmp , Brig::BrigInstCvt , Brig::BrigInstImage , Brig::BrigInstLane , Brig::BrigInstMem , Brig::BrigInstMemFence , Brig::BrigInstMod , Brig::BrigInstQueryImage , Brig::BrigInstQuerySampler , Brig::BrigInstQueue , Brig::BrigInstSeg , Brig::BrigInstSegCvt , Brig::BrigInstSignal , Brig::BrigInstSourceType , Brig::BrigOperandAddress , Brig::BrigOperandAlign , Brig::BrigOperandCodeList , Brig::BrigOperandCodeRef , Brig::BrigOperandConstantBytes , Brig::BrigOperandConstantImage , Brig::BrigOperandConstantOperandList , Brig::BrigOperandConstantSampler , Brig::BrigOperandOperandList , Brig::BrigOperandRegister , Brig::BrigOperandString , Brig::BrigOperandWavesize , cp::Format , EmbeddedPyBind
• Base : GenericISA::DelaySlotPCState< MachInst > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::SimplePCState< MachInst > , GenericISA::UPCState< MachInst > , GlobalEvent , GlobalSyncEvent , HsailISA::Barrier , HsailISA::MemFence , HsailISA::Ret
• base() : MipsISA::MipsFaultBase
• Base : NullISA::PCState , Sinic::Base
• base : TimeBuffer< T > , X86ISA::EmulEnv , X86ISA::I386Process::VSyscallPage , X86ISA::MemOp
• Base : X86ISA::PCState
• base : X86ISA::X86_64Process::VSyscallPage
• base_addr : UserDesc64
• baseAddr : ObjectFile::Section , PCIConfig
• baseaddr : Pl111
• baseAddr : PrdEntry , UFSHostDevice::UFSHCDSGEntry
• baseAddr1 : MemTest
• baseAddr2 : MemTest
• BaseArmKvmCPU() : BaseArmKvmCPU
• BaseBufferArg() : BaseBufferArg
• BaseCache() : BaseCache
• baseCCRegIndex : PhysRegFile
• baseCheck() : Stats::Info
• BaseConfigEntry() : X86ISA::IntelMP::BaseConfigEntry
• baseCpu : ThreadState
• BaseDynInst() : BaseDynInst< Impl >
• BaseDynInstPtr : BaseDynInst< Impl >
• baseEntries : X86ISA::IntelMP::ConfigTable
• baseFilename : CheckpointIn
• baseFloatRegIndex : PhysRegFile
• BaseGdbRegCache() : BaseRemoteGDB::BaseGdbRegCache
• BaseGen() : BaseGen
• BaseGic() : BaseGic
• BaseGlobalEvent : BaseGlobalEvent::BarrierEvent , BaseGlobalEvent
• BaseGlobalEventTemplate() : BaseGlobalEventTemplate< Derived >
• BaseISADevice() : ArmISA::BaseISADevice
• baseIsSP : ArmISA::Memory64
• BaseKvmCPU() : BaseKvmCPU , KvmVM
• BaseKvmTimer() : BaseKvmTimer
• BaseMasterPort() : BaseMasterPort
• BaseMemProbe() : BaseMemProbe
• basename : MathExprPowerModel
• BaseO3CPU() : BaseO3CPU
• BaseO3DynInst() : BaseO3DynInst< Impl >
• BaseOperand() : BaseOperand
• basePC : X86ISA::Decoder
• BasePixelPump() : BasePixelPump
• BasePrefetcher() : BasePrefetcher
• basePtr : MultiLevelPageTable< ISAOps > , Wavefront
• BaseRemoteGDB() : BaseRemoteGDB
• BaseSetAssoc() : BaseSetAssoc
• BaseSimpleCPU() : BaseSimpleCPU
• BaseSlavePort() : BaseSlavePort
• BaseTags() : BaseTags
• BaseTagsCallback() : BaseTagsCallback
• BaseTagsDumpCallback() : BaseTagsDumpCallback
• BaseTLB() : BaseTLB
• baseUpdate() : LTAGE
• BaseXBar() : BaseXBar
• BasicBlock() : BasicBlock
• basicBlock() : ControlFlowInfo
• basicBlocks : ControlFlowInfo
• BasicExtLink() : BasicExtLink
• BasicIntLink() : BasicIntLink
• BasicLink() : BasicLink
• BasicPioDevice() : BasicPioDevice
• BasicRouter() : BasicRouter
• BasicSignal() : BasicSignal
• bb : PowerISA::CondLogicOp
• bbMap : SimPoint
• bc : GPUDynInst
• bcd : Intel8254Timer , Pl111
• bCond : Barrier
• bdelayDoneSeqNum : DefaultDecode< Impl >
• bDiv : MathExpr
• bebo : Pl111
• begin() : AddrRangeMap< V > , PacketFifo , SparcISA::TlbMap , Stats::Output , Stats::Text
• beginLine() : BasePixelPump
• bepo : Pl111
• best : cp::Format
• bf : PowerISA::CondMoveOp
• bfa : PowerISA::CondMoveOp
• BGLoad : Sp804::Timer
• bgr : Pl111
• bi : PowerISA::BranchCond
• bias() : ElfObject , ObjectFile
• big_endian : HDLcd
• bigendian : VncInput::PixelFormat
• BigFpMemImmOp() : ArmISA::BigFpMemImmOp
• BigFpMemLitOp() : ArmISA::BigFpMemLitOp
• BigFpMemPostOp() : ArmISA::BigFpMemPostOp
• BigFpMemPreOp() : ArmISA::BigFpMemPreOp
• BigFpMemRegOp() : ArmISA::BigFpMemRegOp
• bigPkt : TimingSimpleCPU::SplitFragmentSenderState
• bigThumb : ArmISA::Decoder
• BimodalEntry() : LTAGE::BimodalEntry
• bimodalIndex : LTAGE::BranchInfo
• BiModeBP() : BiModeBP
• binary : MathExpr::OpSearch
• BinaryNode() : Stats::BinaryNode< Op >
• binaryOp() : ArmISA::FpOp
• bind() : BaseMasterPort , MasterPort , SlavePort
• bindAllPorts() : CxxConfigManager
• bindex() : LTAGE
• bindList() : OFSchedulingPolicy , RRSchedulingPolicy , Scheduler , SchedulingPolicy< Impl >
• bindMasterPort() : CxxConfigManager
• bindObjectPorts() : CxxConfigManager
• bindPort() : CxxConfigManager
• bindToLoopback : ListenSocket
• bindWaveList() : FetchUnit
• binOp : MathExpr
• BiosInformation() : X86ISA::SMBios::BiosInformation
• bist : PCIConfig
• BitCount : Bitmap::InfoHeaderV1
• bitIndex() : NetDest
• Bitmap() : Bitmap
• bits : ImmOperand< T > , MSIXPbaEntry , Set
• BitUnion32() : ArchTimer , ArmISA::PMU , CpuLocalTimer::Timer , HDLcd , Pl390 , RealViewCtrl , Sp804::Timer , VGic , X86ISA::Interrupts , X86ISA::PageFault
• BitUnion64() : X86ISA::I82094AA
• BitUnion8() : IdeController , Intel8254Timer , MC146818 , Pl050 , Pl111 , VirtIODeviceBase , X86ISA::I8042 , X86ISA::PS2Mouse , X86ISA::Speaker
• BitUnionOperators() : BitfieldBackend::BitUnionOperators< Type, Base >
• blank_space : cp::Format
• bldrev : aout_exechdr
• blk : CacheBlkPrintWrapper
• blkAddr : QueueEntry
• blkAlign() : BaseTags
• blkcnt_t : RiscvLinux
• blkMask : BaseTags
• blks : BaseSetAssoc , CacheSet< Blktype > , FALRU
• blkSize : BaseCache , BasePrefetcher , BaseTags , QueueEntry , UFSHostDevice::UFSSCSIDevice
• blksize_t : RiscvLinux
• BlkType : BaseSetAssoc , FALRU
• Block : ArmISA::TableWalker::LongDescriptor
• block() : DefaultDecode< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FlashDevice::PageMapEntry
• BLOCK_CACHED : Packet
• blockAddress() : BasePrefetcher
• blockAddrMask : MemTest
• blockAlign() : MemTest
• blockBits : DramGen
• BlockBloomFilter() : BlockBloomFilter
• blocked : BaseCache , BaseCache::CacheSlavePort
• Blocked : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• blocked : Minor::Decode::DecodeThreadInfo , Minor::Fetch1::Fetch1ThreadInfo , Minor::Fetch2::Fetch2ThreadInfo
• blocked_causes : BaseCache
• blocked_cycles : BaseCache
• Blocked_NoMSHRs : BaseCache
• Blocked_NoTargets : BaseCache
• Blocked_NoWBBuffers : BaseCache
• BlockedCause : BaseCache
• blockedCycle : BaseCache
• blockedMemInsts : InstructionQueue< Impl >
• blockEmptyEntries : FlashDevice
• blockIndex() : BasePrefetcher
• BlockingInst : BaseDynInst< Impl >
• blockMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• blockOnQueue() : AbstractController
• blockSize : FlashDevice
• blocksize : LinearGen
• blockSize : MemTest
• blocksize : RandomGen , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement
• blockSizeBits : GarnetSyntheticTraffic
• blocksPerDisk : FlashDevice
• blockThisCycle : DefaultRename< Impl >
• blockValidEntries : FlashDevice
• blue : Bitmap::BmpPixel32 , Pixel
• blue_select : HDLcd
• Blue_Select : HDLcd
• bluemax : VncInput::PixelFormat
• blueshift : VncInput::PixelFormat
• bmEnabled : IdeController
• bmiAddr : IdeController
• bmiSize : IdeController
• bmp : HDLcd , Pl111
• bMul : MathExpr
• bMutex : Barrier
• bo : PowerISA::BranchCond
• Bootcs : RealViewCtrl
• bootldr : ArmSystem
• bootLoaders : ArmSystem
• bootReleaseAddr : FreebsdArmSystem
• bottomDW : X86ISA::I82094AA
• bottomReserved : X86ISA::I82094AA
• BoundRange() : X86ISA::BoundRange
• box_tick_cnt : Shader
• bpHistory : BPredUnit::PredictorHistory
• bPow : MathExpr
• bpp : VncInput::PixelFormat
• bpp1 : Pl111
• bpp12 : Pl111
• bpp16 : Pl111
• bpp16m565 : Pl111
• bpp2 : Pl111
• bpp24 : Pl111
• bpp4 : Pl111
• bpp8 : Pl111
• BPredUnit() : BPredUnit
• bpt : PAL
• Branch : DefaultFetch< Impl >
• branchAddr : TimeBufStruct< Impl >::decodeComm
• BranchCond() : PowerISA::BranchCond
• branchCount() : DefaultFetch< Impl > , TimeBufStruct< Impl >::decodeComm
• BranchData() : Minor::BranchData
• BranchEret64() : ArmISA::BranchEret64
• BranchImm() : ArmISA::BranchImm
• BranchImm64() : ArmISA::BranchImm64
• BranchImmCond() : ArmISA::BranchImmCond
• BranchImmCond64() : ArmISA::BranchImmCond64
• BranchImmImmReg64() : ArmISA::BranchImmImmReg64
• BranchImmReg() : ArmISA::BranchImmReg
• BranchImmReg64() : ArmISA::BranchImmReg64
• BranchInfo() : LTAGE::BranchInfo
• branching() : GenericISA::DelaySlotPCState< MachInst > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::SimplePCState< MachInst > , GenericISA::UPCState< MachInst > , X86ISA::PCState
• branchInp : Minor::Fetch2
• branchMispredict : DefaultIEWDefaultCommit< Impl > , TimeBufStruct< Impl >::decodeComm
• branchMispredicts : DefaultCommit< Impl > , DefaultIEW< Impl >
• BranchNonPCRel() : PowerISA::BranchNonPCRel
• BranchNonPCRelCond() : PowerISA::BranchNonPCRelCond
• branchPC : LTAGE::BranchInfo
• BranchPCRel() : PowerISA::BranchPCRel
• BranchPCRelCond() : PowerISA::BranchPCRelCond
• branchPred : BaseSimpleCPU , DefaultFetch< Impl >
• BranchPrediction : Minor::BranchData
• branchPredictor : Minor::Fetch2
• branchRate : DefaultFetch< Impl >
• BranchReg() : ArmISA::BranchReg
• BranchReg64() : ArmISA::BranchReg64
• BranchRegCond() : ArmISA::BranchRegCond , PowerISA::BranchRegCond
• BranchRegReg() : ArmISA::BranchRegReg
• BranchRet64() : ArmISA::BranchRet64
• branchTaken : DefaultIEWDefaultCommit< Impl > , TimeBufStruct< Impl >::commitComm , TimeBufStruct< Impl >::decodeComm
• branchTarget() : ArmISA::BranchImm64 , ArmISA::BranchImmImmReg64 , ArmISA::BranchImmReg64 , BaseDynInst< Impl > , PowerISA::BranchNonPCRel , PowerISA::BranchNonPCRelCond , PowerISA::BranchPCRel , PowerISA::BranchPCRelCond , PowerISA::BranchRegCond , StaticInst
• brar : dp_regs
• BrDirectInst() : HsailISA::BrDirectInst
• brdr : dp_regs
• break_iter_t : BaseRemoteGDB
• break_map_t : BaseRemoteGDB
• break_type() : BaseRemoteGDB
• BreakPCEvent() : BreakPCEvent
• breakpoint() : BaseRemoteGDB , MipsSystem , RiscvSystem , System
• Breakpoint() : X86ISA::Breakpoint
• BreakpointFault() : RiscvISA::BreakpointFault
• Bridge() : Bridge
• bridge : Bridge::BridgeMasterPort , Bridge::BridgeSlavePort
• BridgeMasterPort() : Bridge::BridgeMasterPort
• BridgeSlavePort() : Bridge::BridgeSlavePort
• brigInstBase : HsailISA::MachInst
• brigMajor : Brig::BrigModuleHeader
• brigMinor : Brig::BrigModuleHeader
• brigObj : HsailISA::MachInst
• BrigObject() : BrigObject
• BrigRegOperandInfo() : BrigRegOperandInfo
• brigSymbol : StorageElement
• BrIndirectInst() : HsailISA::BrIndirectInst
• BrInstBase() : HsailISA::BrInstBase< TargetType >
• BrnDirectInst() : HsailISA::BrnDirectInst
• BrnIndirectInst() : HsailISA::BrnIndirectInst
• BrnInstBase() : HsailISA::BrnInstBase< TargetType >
• broadcast() : Net::EthAddr , NetDest , Set
• bsize : aout_exechdr , ecoff_aouthdr
• bss : ObjectFile
• bss_start : aout_exechdr , ecoff_aouthdr
• bssBase() : ObjectFile
• bssSize() : ObjectFile
• bSub : MathExpr
• bt : PowerISA::CondLogicOp , TIR
• btable : LTAGE
• BTB : BPredUnit
• btb : DefaultBTB
• BTBCorrect : BPredUnit
• BTBEntry() : DefaultBTB::BTBEntry
• BTBHitPct : BPredUnit
• BTBHits : BPredUnit
• BTBLookup() : BPredUnit
• BTBLookups : BPredUnit
• btbUpdate() : BiModeBP , BPredUnit
• BTBUpdate() : BPredUnit
• btbUpdate() : LocalBP , LTAGE , TournamentBP
• BTBValid() : BPredUnit
• bubble() : Minor::BranchData , Minor::BubbleTraitsAdaptor< ElemType > , Minor::BubbleTraitsPtrAdaptor< PtrType, ElemType > , Minor::ForwardLineData , Minor::MinorDynInst , Minor::NoBubbleTraits< ElemType > , Minor::QueuedInst
• bubbleFill() : Minor::ForwardInstData
• bubbleFlag : Minor::ForwardLineData
• bubbleInst : Minor::MinorDynInst
• bucket_size : Stats::DistData , Stats::DistStor , Stats::DistStor::Params , Stats::HistStor
• buckets : Stats::DistStor::Params , Stats::HistStor::Params
• buf : CircleBuf< T > , Fifo< T > , iGbReg::RxDesc
• buff_per_vc : FaultModel::system_conf
• buffer : DmaReadFifo , EtherTapBase
• Buffer : Minor::Latch< Data >
• buffer : Minor::Latch< Data > , TimeBuffer< T >::wire , UFSHostDevice::transferInfo , VPtr< T >
• buffer_size : Pl111
• buffer_used : EtherTapStub
• BufferArg() : BufferArg
• bufferData() : X86ISA::PS2Device
• bufferPtr() : BufferArg
• bufferram : AlphaLinux::tgt_sysinfo , ArmLinux32::tgt_sysinfo , ArmLinux64::tgt_sysinfo , MipsLinux::tgt_sysinfo , Sparc32Linux::tgt_sysinfo , SparcLinux::tgt_sysinfo , X86Linux32::tgt_sysinfo , X86Linux64::tgt_sysinfo
• buflen : EtherTapBase
• bufLen() : iGbReg::Regs::SRRCTL
• bufLength : EthPacketData
• bufPtr : BaseBufferArg
• bufptr : ns_desc32 , ns_desc64
• bugchk : PAL
• buildInst() : DefaultFetch< Impl >
• buildPacket() : TimingSimpleCPU
• buildSplitPacket() : TimingSimpleCPU
• BulkBloomFilter() : BulkBloomFilter
• burst_len : HDLcd
• burstAlign() : DRAMCtrl
• burstCount : DRAMCtrl::BurstHelper
• BurstHelper() : DRAMCtrl::BurstHelper
• burstHelper : DRAMCtrl::DRAMPacket
• burstLength : DRAMCtrl
• burstSize : DRAMCtrl , DRAMSim2Wrapper
• burstsServiced : DRAMCtrl::BurstHelper
• bus : EtherBus::DoneEvent , PciBusAddr
• Bus() : X86ISA::IntelMP::Bus
• bus_options : HDLcd
• Bus_Options : HDLcd
• BUS_OPTIONS_RESETV : HDLcd
• busAddr() : PciDevice , PciHost::DeviceInterface
• busBusyUntil : DRAMCtrl
• BusHierarchy() : X86ISA::IntelMP::BusHierarchy
• busID : X86ISA::IntelMP::AddrSpaceMapping , X86ISA::IntelMP::Bus , X86ISA::IntelMP::BusHierarchy , X86ISA::IntelMP::CompatAddrSpaceMod
• busState : DRAMCtrl
• BusState : DRAMCtrl
• busStateNext : DRAMCtrl
• busType : X86ISA::IntelMP::Bus
• busUtil : DRAMCtrl
• busUtilRead : DRAMCtrl
• busUtilWrite : DRAMCtrl
• BUSY : BaseXBar::Layer< SrcType, DstType >
• busy : ConditionRegisterState , CopyEngine::CopyEngineChannel , DistEtherLink::Link , DMASequencer , EtherBus , EtherLink::Link , Iob::IntBusy , Shader , VectorRegisterFile
• busyBanks : BankedArray
• button_mask : VncInput::PointerEventMessage
• bwInstRead : AbstractMemory
• bwRead : AbstractMemory
• bwTotal : AbstractMemory
• bwWrite : AbstractMemory
• bypassCaches() : System
• byte_order : PixelConverter
• byte_trackers : MemChecker
• byteCount : Brig::BrigBase , Brig::BrigData , Brig::BrigModuleHeader , Brig::BrigSectionHeader , PrdEntry
• byteMask : MsrBase
• bytes : Brig::BrigData , Brig::BrigOperandConstantBytes , Net::EthAddr , Net::EthHdr , Net::Ip6Hdr , Net::IpHdr , Net::TcpHdr , Net::TcpOpt , Net::UdpHdr
• bytes_completed : DMARequest
• bytes_issued : DMARequest
• bytes_per_pixel : HDLcd
• bytesAccessed : DRAMCtrl::Bank
• bytesAllocated : LdsState
• bytesCopied : CopyEngine , IGbE::RxDescCache
• bytesInstRead : AbstractMemory
• bytesPerActivate : DRAMCtrl
• bytesPerPixel : Pl111
• bytesRead : AbstractMemory
• bytesReadDRAM : DRAMCtrl
• bytesReadSys : DRAMCtrl
• bytesReadWrQ : DRAMCtrl
• bytesValid : Packet
• bytesWritten : AbstractMemory , DRAMCtrl
• bytesWrittenSys : DRAMCtrl
• ByteTable : X86ISA::Decoder
• ByteTracker() : MemChecker::ByteTracker