Here is a list of all class members with links to the classes they belong to:

- d -

• d : ArmISA::PMU , KvmFPReg , PhysRegFile::PhysFloatReg
• D0 : MipsISA::PTE , PowerISA::PTE , RiscvISA::PTE
• d1 : iGbReg::TxDesc
• D1 : MipsISA::PTE , PowerISA::PTE , RiscvISA::PTE
• d2 : iGbReg::TxDesc
• d_data : GPUDynInst
• d_reg : VecRegisterState
• dacr : ArmISA::TLB
• data() : AlphaISA::RemoteGDB::AlphaGdbRegCache , Arguments
• Data() : Arguments::Data
• data : Arguments::Data , ArmISA::Decoder , ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ArmISA::Stage2MMU::Stage2Translation , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor , BaseRemoteGDB::BaseGdbRegCache , CacheBlk , CommandReg , CowDiskImage::Sector , DmaReadFifo::DmaDoneEvent , DMARequest , EthPacketData , GarnetSyntheticTraffic::GarnetSyntheticTrafficSenderState , GdbCommand::Context , KvmFPReg , LSQUnit< Impl >::SQEntry , MemChecker::Transaction , Minor::LSQ::LSQRequest , MipsISA::RemoteGDB::MipsGdbRegCache , MSICAP , MSIXCAP , MSIXTable , Net::IpOpt , Net::TcpOpt , ObjectFile , Packet , PCIConfig , PMCAP , PowerISA::RemoteGDB::PowerGdbRegCache , PXCAP , RefCountingPtr< T > , RiscvISA::RemoteGDB::RiscvGdbRegCache , RubyRequest , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , Stats::DistBase< Derived, Stor > , Stats::DistInfo , Stats::DistPrint , Stats::DistProxy< Stat > , Stats::ScalarBase< Derived, Stor > , Stats::ScalarStatNode , Stats::SparseHistBase< Derived, Stor > , Stats::SparseHistInfo , Stats::SparseHistPrint , Stats::StatStor , Stats::Vector2dBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor > , Stats::VectorDistInfo , Stats::VectorProxy< Stat > , Stats::VectorStatNode , Terminal , TimeBuffer< T > , Trace::InstRecord , VncServer , WholeTranslationState , X86ISA::LdStOp , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache
• data_accesses : AlphaISA::TLB
• data_acv : AlphaISA::TLB
• data_corruption__all_bits : FaultModel
• data_corruption__few_bits : FaultModel
• data_fd : Terminal
• data_hits : AlphaISA::TLB
• DATA_INITIAL : MemChecker
• data_misses : AlphaISA::TLB
• data_polarity : HDLcd
• data_read_req : AtomicSimpleCPU
• data_start : aout_exechdr , ecoff_aouthdr
• data_status : Trace::InstRecord
• data_write_req : AtomicSimpleCPU
• DataAbort() : ArmISA::DataAbort
• dataAccesses : BaseTags
• dataArray : CacheMemory
• dataAvailable() : Pl011 , Terminal , Uart8250 , Uart
• dataBase() : ObjectFile
• dataBlks : BaseSetAssoc
• DataBlock() : DataBlock
• dataBuffer : IdeDisk
• dataCallback() : DMASequencer
• dataCount : UFSHostDevice::UPIUMessage
• dataDescriptor : DistHeaderPkt
• dataDistribution : FlashDevice
• DataDouble : Trace::InstRecord
• dataDynamic() : Packet
• dataen_polarity : HDLcd
• dataEvent : Terminal
• DataEvent : Terminal , Terminal::DataEvent
• dataEvent : VirtIO9PDiod , VirtIO9PSocket , VncServer
• DataEvent : VncServer , VncServer::DataEvent
• dataFd : VncServer
• dataHi : X86ISA::LdStSplitOp
• DataImmOp() : ArmISA::DataImmOp
• DataInt16 : Trace::InstRecord
• DataInt32 : Trace::InstRecord
• DataInt64 : Trace::InstRecord
• DataInt8 : Trace::InstRecord
• DataInvalid : Trace::InstRecord
• dataLastTick : TraceCPU::ElasticDataGen
• dataLatency : BaseCache
• dataLimit : LinearGen , RandomGen
• dataLow : X86ISA::LdStSplitOp
• dataManipulated : LinearGen , RandomGen
• dataMasterID : TraceCPU
• dataMsg : UFSHostDevice::UPIUMessage
• dataName : Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• dataOffset : UFSHostDevice::UPIUMessage
• dataPacketLength : DistHeaderPkt::Header
• dataPort : BaseKvmCPU
• DataPort() : ComputeUnit::DataPort
• dataPort : ComputeUnit::DataPort::MemReqEvent , ComputeUnit::DataPort::MemRespEvent , X86ISA::I8042
• DataReg : PL031
• dataReg : X86ISA::I8042
• DataRegOp() : ArmISA::DataRegOp
• DataRegRegOp() : ArmISA::DataRegRegOp
• DataSectionIndex : BrigObject
• dataSize : ArmISA::MicroNeonMixLaneOp64 , ArmISA::MicroNeonMixOp64 , ArmISA::VldMultOp64 , ArmISA::VldSingleOp64 , ArmISA::VstMultOp64 , ArmISA::VstSingleOp64 , ObjectFile , X86ISA::EmulEnv , X86ISA::FpOp , X86ISA::MemOp , X86ISA::RegOpBase , X86ISA::Walker::WalkerState
• dataStatic() : Packet
• dataStaticConst() : Packet
• dataTraceFile : TraceCPU
• dataTraceStream : ElasticTrace
• DataTranslation() : DataTranslation< ExecContextPtr >
• DataWrap() : Stats::DataWrap< Derived, InfoProxyType >
• DataWrapVec() : Stats::DataWrapVec< Derived, InfoProxyType >
• DataWrapVec2d< Derived, Vector2dInfoProxy > : Stats::Vector2dBase< Derived, Stor >
• DataWrapVec< Derived, Vector2dInfoProxy > : Stats::Vector2dBase< Derived, Stor >
• DataWrapVec< Derived, VectorDistInfoProxy > : Stats::VectorDistBase< Derived, Stor >
• DataWrapVec< Derived, VectorInfoProxy > : Stats::VectorBase< Derived, Stor >
• DataX1Reg2ImmOp() : ArmISA::DataX1Reg2ImmOp
• DataX1RegImmOp() : ArmISA::DataX1RegImmOp
• DataX1RegOp() : ArmISA::DataX1RegOp
• DataX2RegImmOp() : ArmISA::DataX2RegImmOp
• DataX2RegOp() : ArmISA::DataX2RegOp
• DataX3RegOp() : ArmISA::DataX3RegOp
• DataXCondCompImmOp() : ArmISA::DataXCondCompImmOp
• DataXCondCompRegOp() : ArmISA::DataXCondCompRegOp
• DataXCondSelOp() : ArmISA::DataXCondSelOp
• DataXERegOp() : ArmISA::DataXERegOp
• DataXImmOnlyOp() : ArmISA::DataXImmOnlyOp
• DataXImmOp() : ArmISA::DataXImmOp
• DataXSRegOp() : ArmISA::DataXSRegOp
• date() : Time
• db : CheckpointIn
• dbg_vtophys() : BaseSimpleCPU , CheckerCPU , MinorCPU
• dbgHeader() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor
• dbl() : ArmISA::FpOp , BaseDynInst< Impl >::Result , CheckerCPU::Result
• dblHi() : ArmISA::FpOp
• dblLow() : ArmISA::FpOp
• dcache_access : AtomicSimpleCPU
• dcache_latency : AtomicSimpleCPU
• dcache_pkt : TimingSimpleCPU
• dcacheGen : TraceCPU
• dcacheInterface : InstructionQueue< Impl >
• dcacheNextEvent : TraceCPU
• dcachePort : AtomicSimpleCPU , CheckerCPU , FullO3CPU< Impl >
• DcachePort() : FullO3CPU< Impl >::DcachePort
• dcachePort : LSQUnit< Impl > , Minor::LSQ
• DcachePort() : Minor::LSQ::DcachePort
• dcachePort : TimingSimpleCPU
• DcachePort() : TimingSimpleCPU::DcachePort
• dcachePort : TraceCPU
• DcachePort() : TraceCPU::DcachePort
• dcacheRecvTimingResp() : TraceCPU
• DcacheRetry : BaseSimpleCPU
• dcacheRetryRecvd() : TraceCPU
• dcacheStallCycles : SimpleExecContext
• DcacheWaitResponse : BaseSimpleCPU
• DcacheWaitSwitch : BaseSimpleCPU
• dcc : RealViewCtrl
• deactivateStage() : ActivityRecorder , DefaultIEW< Impl > , FullO3CPU< Impl >
• deactivateThread() : DefaultCommit< Impl > , DefaultFetch< Impl > , FullO3CPU< Impl >
• deadlockCheckEvent : GPUCoalescer , Sequencer
• deallocate() : CacheMemory , MSHR , PerfectCacheMemory< ENTRY > , Queue< Entry > , TBETable< ENTRY > , WriteQueueEntry
• deallocateContext() : BaseKvmCPU
• Debug_Break_Pri : EventBase
• Debug_Enable_Pri : EventBase
• DebugBreakEvent() : DebugBreakEvent
• DebugEvent : ArmISA::ArmFault
• DebugException() : X86ISA::DebugException
• DebugFunc : GenericISA::M5DebugFault
• debugger : BaseRemoteGDB
• debugPrint() : Check
• debugPrintkEvent : ArmSystem
• DebugPrintkEvent() : Linux::DebugPrintkEvent
• debugPrintkEvent : LinuxAlphaSystem
• debugSegFault : ComputeUnit
• debugVerify() : EventQueue
• dec : cp::Format , Stats::AvgStor , Stats::StatStor
• declare_router() : FaultModel
• decode() : AlphaISA::Decoder , ArmISA::Decoder , DefaultDecode< Impl > , DefaultFetch< Impl >::Stalls , FullO3CPU< Impl > , GenericISA::BasicDecodeCache , HsailISA::Decoder
• Decode() : Minor::Decode
• decode : Minor::Pipeline , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder
• Decode : SimpleCPUPolicy< Impl >
• decode() : SparcISA::Decoder , X86ISA::Decoder
• decodeAddr() : DRAMCtrl
• decodeAddress() : GenericPciHost
• decodeBlock : TimeBufStruct< Impl >
• decodeBlockedCycles : DefaultDecode< Impl >
• decodeBranchMispred : DefaultDecode< Impl >
• decodeBranchResolved : DefaultDecode< Impl >
• decodeControlMispred : DefaultDecode< Impl >
• decodeCoProcReg() : ArmKvmCPU
• decodeDecodedInsts : DefaultDecode< Impl >
• decodedInsts : HsailISA::Decoder
• decodeIdleCycles : DefaultDecode< Impl >
• DecodeIdx : FullO3CPU< Impl >
• decodeInfo : Minor::Decode , TimeBufStruct< Impl >
• decodeInst() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• decodeInsts() : DefaultDecode< Impl >
• decodePages : GenericISA::BasicDecodeCache , X86ISA::Decoder
• DecodePages : X86ISA::Decoder
• decodePrologue() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• decodeQueue : DefaultDecode< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• Decoder() : AlphaISA::Decoder , ArmISA::Decoder
• decoder : DefaultFetch< Impl > , FetchUnit , HsailCode
• Decoder() : MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder
• decoder : SimpleThread
• Decoder() : SparcISA::Decoder , X86ISA::Decoder
• DecoderFaultInst() : DecoderFaultInst
• decoderFlavour : ArmISA::Decoder , ArmISA::ISA
• decodeRunCycles : DefaultDecode< Impl >
• decodeSave() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• decodeSquashCycles : DefaultDecode< Impl >
• decodeSquashedInsts : DefaultDecode< Impl >
• decodeStack() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• DecodeStageId : Minor::Pipeline
• decodeStatus : DefaultDecode< Impl >
• DecodeStatus : DefaultDecode< Impl >
• DecodeStruct : DefaultDecode< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , SimpleCPUPolicy< Impl >
• DecodeThreadInfo() : Minor::Decode::DecodeThreadInfo
• decodeToFetchDelay : DefaultFetch< Impl >
• decodeToRenameDelay : DefaultRename< Impl >
• decodeUnblock : TimeBufStruct< Impl >
• decodeUnblockCycles : DefaultDecode< Impl >
• decodeVFPCtrlReg() : ArmKvmCPU
• decodeWidth : DefaultDecode< Impl > , DefaultFetch< Impl >
• decreaseRefCounter() : LdsState
• decref() : RefCounted
• decrement() : AbstractBloomFilter , BlockBloomFilter , BulkBloomFilter , H3BloomFilter , LSB_CountingBloomFilter , MultiBitSelBloomFilter , MultiGrainBloomFilter , NonCountingBloomFilter , SatCounter
• decrement_credit() : OutputUnit , OutVcState
• DecrementAfter : ArmISA::RfeOp , ArmISA::SrsOp
• DecrementBefore : ArmISA::RfeOp , ArmISA::SrsOp
• decrLdIdx() : LSQUnit< Impl >
• decrStIdx() : LSQUnit< Impl >
• decrTos() : ReturnAddrStack
• defAddr : X86ISA::Decoder
• DEFAULT : PseudoInst::InitParamKey
• default_color : HDLcd
• Default_Pri : EventBase
• DefaultBTB() : DefaultBTB
• defaultCache : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder
• DefaultCommit() : DefaultCommit< Impl >
• defaultConfig : X86ISA::IntelMP::FloatingPointer
• DefaultDecode() : DefaultDecode< Impl >
• DefaultFetch() : DefaultFetch< Impl >
• defaultFloatRound : Brig::BrigDirectiveModule
• DefaultIEW() : DefaultIEW< Impl >
• defaultPortID : BaseXBar
• defaultRange : BaseXBar
• DefaultRename() : DefaultRename< Impl >
• DefaultsAndDisable : X86ISA::PS2Keyboard , X86ISA::PS2Mouse
• defCc : ArmISA::DataXCondCompImmOp , ArmISA::DataXCondCompRegOp , ArmISA::FpCondCompRegOp
• deferMemInst() : InstructionQueue< Impl >
• deferredMemInsts : InstructionQueue< Impl >
• DeferredPacket() : Bridge::DeferredPacket , PacketQueue::DeferredPacket , QueuedPrefetcher::DeferredPacket , SerialLink::DeferredPacket , SimpleMemory::DeferredPacket
• DeferredPacketList : PacketQueue
• deferredPacketReady() : PacketQueue
• deferredPacketReadyTime() : PacketQueue
• deferredTargets : MSHR
• define() : Label
• defined() : Label
• defns : TimingExprLet
• defOp : X86ISA::Decoder
• degree : StridePrefetcher , TaggedPrefetcher
• del() : RefCountingPtr< T >
• delay : Bridge::BridgeMasterPort , Bridge::BridgeSlavePort , DmaPort::DmaReqState , Minor::Latch< Data > , SerialLink::SerialLinkMasterPort , SerialLink::SerialLinkSlavePort , WholeTranslationState
• delayed : ArmISA::TableWalker::WalkerState
• Delayed_Writeback_Pri : EventBase
• delayedCommit : DefaultFetch< Impl >
• delayedStartup() : KvmVM
• delayHead() : MessageBuffer
• delayHistogram : Profiler
• delayIntEvent() : IGbE
• DelaySlotPCState() : GenericISA::DelaySlotPCState< MachInst >
• DelaySlotUPCState() : GenericISA::DelaySlotUPCState< MachInst >
• delayVar : DistEtherLink::TxLink , EtherLink::Link , EtherSwitch::Interface
• delayVCHistogram : Profiler
• deleteData() : Packet
• deleteObjects() : CxxConfigManager
• deleteReqs() : WholeTranslationState
• deleteRequest() : Minor::LSQ::StoreBuffer
• deliverInterrupts() : X86KvmCPU
• deliveryMode : X86ISA::I82094AA , X86ISA::Interrupts
• deliveryStatus : X86ISA::I82094AA
• delta : TraceCPU::FixedRetryGen
• demandAccesses : BaseCache
• demandAvgMissLatency : BaseCache
• demandAvgMshrMissLatency : BaseCache
• demandHits : BaseCache
• demandMisses : BaseCache
• demandMissLatency : BaseCache
• demandMissRate : BaseCache
• demandMshrHits : BaseCache
• demandMshrMisses : BaseCache
• demandMshrMissLatency : BaseCache
• demandMshrMissRate : BaseCache
• demandReserve : MSHRQueue
• demapAll() : SparcISA::TLB
• demapContext() : SparcISA::TLB
• demapDataPage() : BaseDynInst< Impl > , CheckerCPU , FullO3CPU< Impl > , Minor::ExecContext , SimpleThread
• demapInstPage() : BaseDynInst< Impl > , CheckerCPU , FullO3CPU< Impl > , Minor::ExecContext , SimpleThread
• demapPage() : AlphaISA::TLB , ArmISA::TLB , BaseDynInst< Impl > , BaseTLB , CheckerCPU , ExecContext , FullO3CPU< Impl > , GenericTLB , Minor::ExecContext , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SimpleExecContext , SimpleThread , SparcISA::TLB , X86ISA::GpuTLB , X86ISA::TLB
• depCheckShift : LSQUnit< Impl >
• DependencyEntry() : DependencyEntry< DynInstPtr >
• DependencyGraph() : DependencyGraph< DynInstPtr >
• dependents : TraceCPU::ElasticDataGen::GraphNode
• dependGraph : DependencyGraph< DynInstPtr > , InstructionQueue< Impl >
• dependInsts : MemDepUnit< MemDepPred, Impl >::MemDepEntry
• depends : HsaQueueEntry
• DepEntry : DependencyGraph< DynInstPtr >
• depFreeQueue : TraceCPU::ElasticDataGen
• depGraph : TraceCPU::ElasticDataGen
• depPred : MemDepUnit< MemDepPred, Impl >
• depsReady() : EmbeddedPyBind
• depth : Brig::BrigOperandConstantImage , PixelConverter , Request , VncInput::PixelFormat
• depTrace : ElasticTrace
• depTraceItr : ElasticTrace
• depTraceRevItr : ElasticTrace
• depWindowSize : ElasticTrace
• dequeue() : MessageBuffer , SimpleMemory , WireBuffer
• dequeueCallback() : NetworkInterface
• dequeueEvent : SimpleMemory
• DerivedClockDomain() : DerivedClockDomain
• DerivO3CPU() : DerivO3CPU
• desc() : Debug::Flag
• Desc() : DistIface::RecvScheduler::Desc
• desc() : Stats::DataWrap< Derived, InfoProxyType > , Stats::DistPrint , Stats::Info , Stats::ScalarPrint , Stats::SparseHistPrint , Stats::VectorPrint , VirtDescriptor , vring
• descBase() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• DescCache() : IGbE::DescCache< T >
• descChainAddr : CopyEngineReg::ChanRegs
• descDmaRdBytes : EtherDevice
• descDmaReads : EtherDevice
• descDmaWrBytes : EtherDevice
• descDmaWrites : EtherDevice
• descEnd : IGbE::TxDescCache
• descHead() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• deschedule() : BaseGlobalEvent , EventManager , EventQueue , LdsState::TickEvent
• descheduleDeadlockEvent() : DMASequencer , GPUCoalescer , RubyPort , RubyPortProxy , Sequencer
• descheduleInstCommitEvent() : BaseRemoteGDB
• descInBlock() : IGbE::TxDescCache
• descLeft() : IGbE::DescCache< T >
• descLen() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• descQueue : DistIface::RecvScheduler
• descr() : PCEvent
• describe() : X86ISA::PageFault , X86ISA::X86FaultBase
• description() : AtomicSimpleCPU::TickEvent , BaseGlobalEvent , BaseKvmCPU::TickEvent , ComputeUnit::DataPort::MemReqEvent , ComputeUnit::DataPort::MemRespEvent , CountedExitEvent , DebugBreakEvent , DefaultCommit< Impl >::TrapEvent , DefaultFetch< Impl >::FinishTranslationEvent , EndQuiesceEvent , EtherBus::DoneEvent , EtherTapBase::TxEvent , Event , EventWrapper< T, F > , FullO3CPU< Impl >::TickEvent , GarnetSyntheticTraffic::TickEvent , GlobalSimLoopExitEvent , GlobalSyncEvent , GPUCoalescer::GPUCoalescerWakeupEvent , GPUCoalescer::IssueEvent , GpuDispatcher::TickEvent , InstructionQueue< Impl >::FUCompletion , Intel8254Timer::Counter::CounterEvent , LocalSimLoopExitEvent , LSQUnit< Impl >::WritebackEvent , MC146818::RTCEvent , MC146818::RTCTickEvent , Minor::FUPipeline , MinorFUTiming , MipsISA::ISA::CP0Event , PCEvent , Pl390::PostIntEvent , RubyDirectedTester::DirectedStartEvent , RubyTester::CheckStartEvent , Sequencer::SequencerWakeupEvent , Shader::TickEvent , Stats::StatEvent , TimingSimpleCPU::DcachePort::DTickEvent , TimingSimpleCPU::IcachePort::ITickEvent , TimingSimpleCPU::IprEvent , TimingSimpleCPU::TimingCPUPort::TickEvent , TLBCoalescer::CleanupEvent , TLBCoalescer::IssueProbeEvent , Uart8250::IntrEvent , VGic::PostVIntEvent , X86ISA::GpuTLB::TLBEvent
• descriptions : Stats::DistPrint , Stats::ScalarPrint , Stats::SparseHistPrint , Stats::Text , Stats::VectorPrint
• DescriptorFetch : CopyEngine::CopyEngineChannel
• descriptors : VirtQueue
• descs : ArmFreebsdProcessBits::SyscallTable , ArmLinuxProcessBits::SyscallTable
• descSize() : iGbReg::Regs::RCTL
• descTail() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• descUnused() : IGbE::DescCache< T >
• descUsed() : IGbE::DescCache< T >
• dest : ArmISA::DataImmOp , ArmISA::DataRegOp , ArmISA::DataRegRegOp , ArmISA::DataX1Reg2ImmOp , ArmISA::DataX1RegImmOp , ArmISA::DataX1RegOp , ArmISA::DataX2RegImmOp , ArmISA::DataX2RegOp , ArmISA::DataX3RegOp , ArmISA::DataXCondSelOp , ArmISA::DataXERegOp , ArmISA::DataXImmOnlyOp , ArmISA::DataXImmOp , ArmISA::DataXSRegOp , ArmISA::FpCondSelOp , ArmISA::FpRegImmOp , ArmISA::FpRegRegImmOp , ArmISA::FpRegRegOp , ArmISA::FpRegRegRegCondOp , ArmISA::FpRegRegRegImmOp , ArmISA::FpRegRegRegOp , ArmISA::FpRegRegRegRegOp , ArmISA::Memory64 , ArmISA::Memory , ArmISA::MicroMemPairOp , ArmISA::MicroNeonMemOp , ArmISA::MicroNeonMixLaneOp64 , ArmISA::MicroNeonMixOp64 , ArmISA::MicroNeonMixOp , ArmISA::Swap , ArmISA::SysDC64 , CopyEngineReg::DmaDesc , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::Call , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , McrrOp , MiscRegRegImmOp , MrrcOp , MrsOp , RegImmImmOp , RegImmOp , RegImmRegOp , RegImmRegShiftOp , RegMiscRegImmOp , RegRegImmImmOp64 , RegRegImmImmOp , RegRegImmOp , RegRegOp , RegRegRegImmOp64 , RegRegRegImmOp , RegRegRegOp , RegRegRegRegOp , X86ISA::FpOp , X86ISA::I82094AA , X86ISA::MediaOpBase , X86ISA::RegOpBase
• dest2 : ArmISA::MemoryDImm64 , ArmISA::MemoryDImm , ArmISA::MemoryDReg , ArmISA::MicroMemPairOp , MrrcOp
• dest_ni : RouteInfo
• dest_router : RouteInfo
• dest_vect : HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
• destApicID : X86ISA::IntelMP::IntAssignment
• destApicIntIn : X86ISA::IntelMP::IntAssignment
• DestCType : HsailISA::SpecialInst1Src< DestDataType > , HsailISA::SpecialInstNoSrc< DestDataType > , HsailISA::ThreeNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType, Src2DataType > , HsailISA::TwoNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType >
• destination : UFSHostDevice::SCSIResumeInfo , UFSHostDevice::taskStart , UFSHostDevice::transferDoneInfo , UFSHostDevice::transferStart
• destMode : X86ISA::I82094AA
• DestOperand : HsailISA::HsailOperandType< _DestOperand, _SrcOperand >
• destRegIdx() : BaseDynInst< Impl > , StaticInst
• destroyStreams() : ProtoInputStream
• destSize : X86ISA::MediaOpBase
• detach() : BaseRemoteGDB , EtherTapStub , PerfKvmCounter , Terminal , VncServer
• dev : IGbEInt , NSGigEInt , PciBusAddr , RealViewCtrl , Sinic::Interface
• dev_mondo_head : SparcISA::ISA
• dev_mondo_tail : SparcISA::ISA
• dev_t : RiscvLinux , Solaris
• Device : ArmISA::TlbEntry
• device : DmaPort , PCIConfig , PioPort
• Device() : RealViewCtrl::Device , Sinic::Device
• device : X86ISA::IntDevice::IntMasterPort , X86ISA::IntDevice::IntSlavePort , X86ISA::IntSinkPin
• DEVICE_SCOPE : Request
• deviceBusWidth : DRAMCtrl
• DeviceFDEntry() : DeviceFDEntry
• deviceFeatures : VirtIODeviceBase
• DeviceFunc : RealViewCtrl
• DeviceId : Iob , VirtIODeviceBase
• deviceId : VirtIODeviceBase
• DeviceInterface() : PciHost::DeviceInterface
• DeviceNotAvailable() : X86ISA::DeviceNotAvailable
• deviceReadCallback : UFSHostDevice::UFSSCSIDevice
• deviceRowBufferSize : DRAMCtrl
• devices : I2CBus , PciHost , RealViewCtrl
• deviceSize : DRAMCtrl
• devicesPerRank : DRAMCtrl
• deviceTiming : IdeController
• deviceUsed : VirtIO9PProxy
• devID : IdeDisk
• devIntrChangeMask() : NSGigE , Sinic::Device
• devIntrClear() : NSGigE , Sinic::Device
• devIntrPost() : NSGigE , Sinic::Device
• devlist : EtherBus
• devlist_t : EtherBus
• devname : BadDevice
• devState : IdeDisk
• DiagnosticDump : X86ISA::I8042
• DiagnosticEcho : X86ISA::PS2Keyboard
• dict_len : DmesgEntry
• digit2i() : BaseRemoteGDB
• dim : Brig::BrigDirectiveVariable , TsunamiCChip
• diod_pid : VirtIO9PDiod
• DiodDataEvent() : VirtIO9PDiod::DiodDataEvent
• dir() : CheckpointIn , LTAGE::LoopEntry , OutputDirectory , TsunamiCChip
• dir_map_t : OutputDirectory
• DirectedGenerator() : DirectedGenerator
• directedStartEvent : RubyDirectedTester
• DirectedStartEvent() : RubyDirectedTester::DirectedStartEvent
• directory() : OutputDirectory
• DirectoryMemory() : DirectoryMemory
• directToStage2 : ArmISA::TLB
• dirs : OutputDirectory
• dirty() : ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor , MmDisk
• DirVarToSE_map : StorageSpace
• disable() : Debug::AllFlags , Debug::CompoundFlag , Debug::Flag , Debug::SimpleFlag , PollEvent
• Disable : X86ISA::PS2Keyboard
• DisableA20 : X86ISA::I8042
• disableAddrDists : CommMonitor::MonitorStats
• disableAll() : Debug::SimpleFlag , ListenSocket
• disableBandwidthHists : CommMonitor::MonitorStats
• disableBurstLengthHists : CommMonitor::MonitorStats
• disableCoalescing : TLBCoalescer
• disabled : ArmISA::UndefinedInstruction , PerfKvmCounterConfig
• disabledFault() : ArmISA::ArmStaticInst
• disableITTDists : CommMonitor::MonitorStats
• DisableKeyboard : X86ISA::I8042
• disableKeyboard : X86ISA::I8042
• disableLatencyHists : CommMonitor::MonitorStats
• disableLinearHists : StackDistProbe
• disableLogHists : StackDistProbe
• disableMemSlot() : KvmVM
• disableMouse : X86ISA::I8042
• DisableMouse : X86ISA::I8042
• disableOutstandingHists : CommMonitor::MonitorStats
• DisableReporting : X86ISA::PS2Mouse
• disableSanityCheck() : PacketQueue
• disableTransactionHists : CommMonitor::MonitorStats
• disarm() : BaseKvmTimer , PerfKvmTimer , PosixKvmTimer
• disassemble() : AddrOperandBase , CRegOperand , DRegOperand , FunctionRefOperand , GPUDynInst , GPUStaticInst , ImmOperand< T > , LabelOperand , ListOperand , NoRegAddrOperand , PowerISA::PCDependentDisassembly , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T > , SRegOperand , StaticInst
• disassembly : GPUStaticInst
• discardFetch() : Wavefront
• discardLeft : StackDistCalc::Node
• discardPendingSignal() : BaseKvmCPU
• discardRight : StackDistCalc::Node
• disk : AlphaBackdoor
• disk_size : RawDiskImage
• diskBlock : AlphaAccess , MipsAccess
• diskCount : AlphaAccess , MipsAccess
• diskData : MmDisk
• diskDelay : IdeDisk
• DiskImage() : DiskImage
• diskOperation : AlphaAccess , MipsAccess
• diskPAddr : AlphaAccess , MipsAccess
• diskSize : FlashDevice , UFSHostDevice::UFSSCSIDevice
• diskUnit : AlphaAccess , MipsAccess
• disp : PowerISA::BranchPCRel , PowerISA::BranchPCRelCond , PowerISA::MemDispOp , X86ISA::MemOp
• dispatch() : DefaultIEW< Impl >
• dispatch_workgroups() : Shader
• dispatchAccess() : IdeController
• dispatchActive : GpuDispatcher
• dispatchCount : GpuDispatcher
• dispatched : TimeBufStruct< Impl >::iewComm
• dispatchedToLQ : TimeBufStruct< Impl >::iewComm
• dispatchedToSQ : TimeBufStruct< Impl >::iewComm
• dispatcher : ClDriver , GpuDispatcher::TickEvent , GpuDispatcher::TLBPort , Shader
• dispatchId : NDRange , Wavefront
• dispatchInsts() : DefaultIEW< Impl >
• dispatchList : ComputeUnit , ExecStage , ScheduleStage
• dispatchStatus : DefaultIEW< Impl >
• dispatchWidth : DefaultIEW< Impl >
• displacement : X86ISA::ExtMachInst
• displacementSize : X86ISA::Decoder
• DisplacementState : X86ISA::Decoder
• DisplayTimings() : DisplayTimings
• displayTimings() : HDLcd
• dispSize : X86ISA::ExtMachInst
• DIST_RANK : PseudoInst::InitParamKey
• DIST_SIZE : Pl390 , PseudoInst::InitParamKey
• DistBase() : Stats::DistBase< Derived, Stor >
• DistEtherLink() : DistEtherLink
• DistHeaderPkt() : DistHeaderPkt
• distIface : DistEtherLink , DistEtherLink::Link
• DistIface() : DistIface
• distIfaceId : DistIface , TCPIface::NodeInfo
• distIfaceNum : DistIface , TCPIface::NodeInfo
• DistInfoProxy() : Stats::DistInfoProxy< Stat >
• DistParams() : Stats::DistParams
• distPioDelay : Pl390
• DistPrint() : Stats::DistPrint
• DistProxy() : Stats::DistProxy< Stat >
• DistProxy< Derived > : Stats::VectorDistBase< Derived, Stor >
• distRange : KvmKernelGicV2
• DistStor() : Stats::DistStor
• DivideError() : X86ISA::DivideError
• DLAB : Uart8250
• dm : MC146818
• dmaAborted : IdeDisk
• dmaAction() : DmaPort
• dmaAddr() : GenericPciHost , PciHost::DeviceInterface , PciHost , TsunamiPChip
• dmaBuffer : Pl111
• DmaCallback() : DmaCallback
• dmaCap1 : IdeController
• DmaChunkEvent() : DmaCallback::DmaChunkEvent
• dmaDataFree : NSGigE
• dmaDescFree : NSGigE
• DmaDevice() : DmaDevice
• dmaDone() : DmaReadFifo , Pl111
• DmaDoneEvent() : DmaReadFifo::DmaDoneEvent , Pl111
• dmaDoneEventAll : Pl111
• dmaDoneEventFree : Pl111
• DmaDoneEventUPtr : DmaReadFifo
• dmaEngine : HDLcd
• DmaEngine() : HDLcd::DmaEngine
• dmaError : IdeController
• dmaIdle : NSGigE
• dmaPending() : DmaDevice , DmaPort
• dmaPendingNum : Pl111
• dmaPort : DmaDevice
• DmaPort() : DmaPort
• dmaPrdReadDone() : IdeDisk
• dmaPrdReadEvent : IdeDisk
• DMARead : CopyEngine::CopyEngineChannel
• dmaRead() : DmaDevice , IdeDisk
• dmaReadBytes : IdeDisk
• dmaReadCG : IdeDisk
• dmaReadDelay : NSGigE , Sinic::Device
• dmaReadDone() : IdeDisk
• dmaReadEvent : IdeDisk
• dmaReadFactor : NSGigE , Sinic::Device
• DmaReadFifo() : DmaReadFifo
• dmaReadFullPages : IdeDisk
• dmaReading : NSGigE
• dmaReadTxs : IdeDisk
• dmaReadWaitEvent : IdeDisk
• dmaReadWaiting : NSGigE
• DmaReqState() : DmaPort::DmaReqState
• DMARequest() : DMARequest
• DMASequencer() : DMASequencer
• dmaSize : Pl111
• dmaState : IdeDisk
• DmaState : NSGigE
• dmaTransferEvent : IdeDisk
• DMAWrite : CopyEngine::CopyEngineChannel
• dmaWrite() : DmaDevice
• dmaWriteBytes : IdeDisk
• dmaWriteCG : IdeDisk
• dmaWriteDelay : NSGigE , Sinic::Device
• dmaWriteDone() : IdeDisk
• dmaWriteEvent : IdeDisk
• dmaWriteFactor : NSGigE , Sinic::Device
• dmaWriteFullPages : IdeDisk
• dmaWriteInfo : UFSHostDevice
• dmaWriteTxs : IdeDisk
• dmaWriteWaitEvent : IdeDisk
• dmaWriteWaiting : NSGigE
• dmaWriting : NSGigE
• dmDrain() : Drainable
• dmDrainResume() : Drainable
• DmesgDumpEvent() : Linux::DmesgDumpEvent
• dnHigh : AUXU
• dnLow : AUXU
• doCalibrateClocks() : FreebsdAlphaSystem
• doCkpt : DistIface::Sync
• doDisplacementState() : X86ISA::Decoder
• doDmaDataRead() : IdeDisk
• doDmaDataWrite() : IdeDisk
• doDmaRead() : IdeDisk
• doDmaTransfer() : IdeDisk
• doDmaWrite() : IdeDisk
• doDRAMAccess() : DRAMCtrl
• doExit : DistIface::Sync
• doFastWrites : Cache
• doFromCacheState() : X86ISA::Decoder
• doFunctionalAccess() : Shader
• doImmediateState() : X86ISA::Decoder
• doingStage2 : ArmISA::TableWalker::WalkerState
• doInit() : Stats::DistBase< Derived, Stor > , Stats::ScalarBase< Derived, Stor > , Stats::SparseHistBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor >
• doInstCommitAccounting() : Minor::Execute
• doL0LongDescEvent : ArmISA::TableWalker
• doL0LongDescriptorWrapper() : ArmISA::TableWalker
• doL1DescEvent : ArmISA::TableWalker
• doL1Descriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doL1DescriptorWrapper() : ArmISA::TableWalker
• doL1LongDescEvent : ArmISA::TableWalker
• doL1LongDescriptorWrapper() : ArmISA::TableWalker
• doL2DescEvent : ArmISA::TableWalker
• doL2Descriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doL2DescriptorWrapper() : ArmISA::TableWalker
• doL2LongDescEvent : ArmISA::TableWalker
• doL2LongDescriptorWrapper() : ArmISA::TableWalker
• doL3LongDescEvent : ArmISA::TableWalker
• doL3LongDescriptorWrapper() : ArmISA::TableWalker
• doLongDescriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doLongDescriptorWrapper() : ArmISA::TableWalker
• domain : ArmISA::AbortFault< T > , ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor , ArmISA::TlbEntry
• DOMAIN_ID : EnergyCtrl
• domainFaults : ArmISA::TLB
• DomainID : DVFSHandler
• domainID() : DVFSHandler , EnergyCtrl , SrcClockDomain
• DomainID : SrcClockDomain
• domainIDIndexToRead : EnergyCtrl
• domainIDList : DVFSHandler
• domainIDToSet : DVFSHandler::UpdateEvent
• DomainLL : ArmISA::ArmFault
• domains : DVFSHandler
• Domains : DVFSHandler
• domains : ThermalModel
• DomainType : ArmISA::TlbEntry
• domatch() : ObjectMatch
• doMMIOAccess() : BaseKvmCPU
• doMmuRegRead() : SparcISA::TLB , X86ISA::GpuTLB
• doMmuRegWrite() : SparcISA::TLB , X86ISA::GpuTLB
• doModRM() : X86ISA::EmulEnv
• doModRMState() : X86ISA::Decoder
• done : _cl_event , ChunkGenerator , DmaReadFifo::DmaDoneEvent , UFSHostDevice::SCSIResumeInfo , UFSHostDevice::taskStart , UFSHostDevice::transferStart
• doneEACalc() : BaseDynInst< Impl >
• doneEvent() : DistEtherLink::RxLink
• DoneEvent : DistEtherLink::RxLink
• doneEvent : DistEtherLink::TxLink
• DoneEvent : DistEtherLink::TxLink , EtherBus::DoneEvent , EtherLink::Link
• doneEvent : EtherLink::Link
• DoneEvent::process : DistEtherLink::RxLink , DistEtherLink::TxLink , EtherLink::Link
• doneIds : GpuDispatcher
• doneSeqNum : TimeBufStruct< Impl >::commitComm , TimeBufStruct< Impl >::decodeComm
• doneSquashing : ROB< Impl >
• doneTargCalc() : BaseDynInst< Impl >
• doOneByteOpcodeState() : X86ISA::Decoder
• doOp() : ArmISA::FpOp
• doPrefixState() : X86ISA::Decoder
• doProcessEvent : ArmISA::TableWalker
• doResetState() : X86ISA::Decoder
• doRetry() : GarnetSyntheticTraffic
• doRxDmaRead() : NSGigE
• doRxDmaWrite() : NSGigE
• doService() : PCEventQueue
• doSIBState() : X86ISA::Decoder
• doSmReturn() : ComputeUnit
• doSquash() : DefaultFetch< Impl > , DefaultRename< Impl > , InstructionQueue< Impl > , ROB< Impl >
• doStep() : ThermalModel
• doStopSync : DistIface::Sync
• doSyscall() : SyscallDesc
• doThreeByte0F38OpcodeState() : X86ISA::Decoder
• doThreeByte0F3AOpcodeState() : X86ISA::Decoder
• doTimingSupplyResponse() : Cache
• doTwoByteOpcodeState() : X86ISA::Decoder
• doTxDmaRead() : NSGigE
• doTxDmaWrite() : NSGigE
• doubleBinSize() : Histogram
• DoubleFault() : X86ISA::DoubleFault
• doVex2Of2State() : X86ISA::Decoder
• doVex2Of3State() : X86ISA::Decoder
• doVex3Of3State() : X86ISA::Decoder
• doVexOpcodeState() : X86ISA::Decoder
• down_flag : VncInput::KeyEventMessage
• downCounter : CountedExitEvent
• downgrade() : StoreTrace
• downstreamPending : MSHR
• doWritebacks() : Cache
• doWritebacksAtomic() : Cache
• dp : ArmISA::PMU
• dpBypassLength() : ComputeUnit
• dpBypassPipeLength : ComputeUnit
• dport() : Net::TcpHdr , Net::UdpHdr
• dprintf() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , SparcISA::StackTrace , Trace::Logger , X86ISA::StackTrace
• drain() : ArmISA::TableWalker , AtomicSimpleCPU , BaseKvmCPU , BasePixelPump::PixelEvent , BaseXBar::Layer< SrcType, DstType > , CopyEngine::CopyEngineChannel , CxxConfigManager , DefaultCommit< Impl > , DefaultFetch< Impl >::Stalls , DistIface , DmaCallback , DmaPort , DmaReadFifo , Drainable , DRAMCtrl , DRAMSim2 , FlashDevice , FullO3CPU< Impl > , IGbE , Minor::Execute , Minor::Pipeline , MinorCPU , MuxingKvmGic , PacketQueue , Pl390 , Process , Queue< Entry > , RubyPort , SimObject , SimpleMemory , TimingSimpleCPU , TrafficGen , UFSHostDevice
• draina : PAL
• Drainable() : Drainable
• drainableCount() : DrainManager
• DrainAllInsts : Minor::Execute
• drainComplete() : DistIface::Sync
• DrainCurrentInst : Minor::Execute
• DrainHaltFetch : Minor::Execute
• drainImminent : DefaultCommit< Impl >
• draining() : DistIface::SyncEvent
• DrainManager : Drainable , DrainManager
• drainPending : DefaultCommit< Impl >
• drainResume() : ArmISA::PMU , ArmISA::TableWalker , ArmISA::TLB , AtomicSimpleCPU , BaseKvmCPU , BasePixelPump::PixelEvent , CopyEngine::CopyEngineChannel , CxxConfigManager , DefaultCommit< Impl > , DefaultFetch< Impl > , DistIface , Drainable , DRAMCtrl , FullO3CPU< Impl > , HDLcd , IGbE , Minor::Execute , Minor::Pipeline , MinorCPU , MuxingKvmGic , NSGigE , RubySystem , Sinic::Device , System , TimingSimpleCPU
• drainSanityCheck() : BPredUnit , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , ROB< Impl >
• drainStall() : DefaultFetch< Impl >
• drainState() : Drainable
• DrainState : Minor::Execute
• drainState : Minor::Execute::ExecuteThreadInfo
• DRAMCtrl() : DRAMCtrl
• DramGen() : DramGen
• DRAMPacket() : DRAMCtrl::DRAMPacket
• DRAMPower() : DRAMPower
• DramRotGen() : DramRotGen
• dramsim : DRAMSim2Wrapper
• DRAMSim2() : DRAMSim2
• DRAMSim2Wrapper() : DRAMSim2Wrapper
• dRegCount : HsaKernelInfo , HsaQueueEntry
• drir : TsunamiCChip
• drive : CommandReg
• driveID : IdeDisk
• driveIrqEn() : Pl390
• driveLegFIQ() : Pl390
• driveLegIRQ() : Pl390
• driver : GpuDispatcher , VirtIODeviceBase
• driver_ok : VirtIODeviceBase
• driverInitialized : Pl050
• drivers : Process
• driveSPI() : Pl390
• dropFetch : Wavefront
• droppedPackets : EtherDevice
• drqBytesLeft : IdeDisk
• ds : X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache
• dse : MC146818
• dsize : aout_exechdr , ecoff_aouthdr
• dst() : Net::EthHdr , Net::Ip6Hdr , Net::IpHdr
• dst_inport_dirn : LinkEntry
• dst_reg : GPUDynInst
• dst_reg_vec : GPUDynInst
• dstOptAddr() : Net::Ip6Opt
• dstOptExt() : Net::Ip6Hdr
• dstOptLength() : Net::Ip6Opt
• dstOpts : Net::ip6_opt_hdr
• dstOptType() : Net::Ip6Opt
• dstRegOpDist : Wavefront
• dtb : CheckerCPU , FullO3CPU< Impl > , SimpleThread
• DtbAcvFault() : AlphaISA::DtbAcvFault
• DtbAlignmentFault() : AlphaISA::DtbAlignmentFault
• DtbFault() : AlphaISA::DtbFault
• DtbObject() : DtbObject
• DtbPageFault() : AlphaISA::DtbPageFault
• DTBWaitResponse : BaseSimpleCPU
• DTickEvent() : TimingSimpleCPU::DcachePort::DTickEvent
• DTLBPort() : ComputeUnit::DTLBPort
• dToE : Minor::Pipeline
• DumbTOD() : DumbTOD
• dummy : FrameBuffer , PowerISA::ISA , X86ISA::Decoder
• DummyChecker() : DummyChecker
• dummyDevice : ArmISA::ISA
• dummyInst : ROB< Impl >
• DummyISADevice() : ArmISA::DummyISADevice
• dump() : ActivityRecorder , ArmKvmCPU , ArmV8KvmCPU , BaseDynInst< Impl > , BaseKvmCPU , BPredUnit , DependencyGraph< DynInstPtr > , DistEtherLink::Link , EtherBus , EtherDump , EtherLink::Link , EtherTapBase , Event , EventQueue , FunctionProfile , FUPool , IniFile , IniFile::Section , PCEventQueue , ProfileNode , Stats::StatEvent , StoreSet , Trace::ExeTracerRecord , Trace::InstPBTraceRecord , Trace::InstRecord , Trace::IntelTraceRecord , Trace::Logger , Trace::NativeTraceRecord , Trie< Key, Value > , Trie< Key, Value >::Node , VirtDescriptor , VirtQueue , X86KvmCPU
• dumpAll() : SparcISA::TLB , X86ISA::GpuTLB
• dumpAllInput() : Minor::Fetch2
• dumpAndExit() : Checker< Impl > , CheckerCPU
• dumpChain() : VirtDescriptor
• dumpDebugRegs() : X86KvmCPU
• dumpDmesg() : LinuxArmSystem
• dumpFpuRegs() : X86KvmCPU
• dumpFuncProfile() : CheckerThreadContext< TC > , O3ThreadContext< class > , O3ThreadState< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext , ThreadState
• dumpHistory() : DefaultRename< Impl >
• dumpInsts() : Checker< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl >
• dumpIntRegs() : X86KvmCPU
• dumpKvmStateCoProc() : ArmKvmCPU
• dumpKvmStateCore() : ArmKvmCPU
• dumpKvmStateMisc() : ArmKvmCPU
• dumpKvmStateVFP() : ArmKvmCPU
• dumpLists() : InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl >
• dumpMsg() : VirtIO9PBase
• dumpMSRs() : X86KvmCPU
• dumpPacket() : EtherDump
• dumpSettings() : HDLcd::DmaEngine , HDLcd::PixelPump
• dumpSpecRegs() : X86KvmCPU
• DumpStatsPCEvent() : DumpStatsPCEvent
• dumpStatsPCEvent : LinuxArmSystem
• dumpTicks() : Trace::ExeTracerRecord
• dumpVCpuEvents() : X86KvmCPU
• dumpXCRs() : X86KvmCPU
• dumpXSave() : X86KvmCPU
• duration : BaseGen
• dv : MC146818
• DVFS_DOMAINID_AT_INDEX : EnergyCtrl
• DVFS_HANDLER_STATUS : EnergyCtrl
• DVFS_HANDLER_TRANS_LATENCY : EnergyCtrl
• DVFS_NUM_DOMAINS : EnergyCtrl
• DVFS_Update_Pri : EventBase
• DVFSHandler() : DVFSHandler
• dvfsHandler : DVFSHandler::UpdateEvent , EnergyCtrl
• dWord0 : UFSHostDevice::LUNInfo , UFSHostDevice::UTPTransferReqDesc::RequestDescHeader , UFSHostDevice::UTPUPIUHeader
• dWord1 : UFSHostDevice::LUNInfo , UFSHostDevice::UTPTransferReqDesc::RequestDescHeader , UFSHostDevice::UTPUPIUHeader
• dWord2 : UFSHostDevice::UTPTransferReqDesc::RequestDescHeader , UFSHostDevice::UTPUPIUHeader
• dWord3 : UFSHostDevice::UTPTransferReqDesc::RequestDescHeader
• dyn_expr : MathExprPowerModel
• Dynamic : InstructionQueue< Impl > , LSQ< Impl > , ROB< Impl >
• DYNAMIC_DATA : Packet
• dynamic_id_count : GPUStaticInst
• dynamicGMemInstrCnt : ComputeUnit
• dynamicLMemInstrCnt : ComputeUnit
• dynamicPower : PowerModel , PowerModelState
• DynInst : DefaultFetch< Impl > , O3CPUImpl
• DynInstPtr : BaseDynInst< Impl > , Checker< Impl > , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultDecodeDefaultRename< Impl > , DefaultFetch< Impl > , DefaultFetchDefaultDecode< Impl > , DefaultIEW< Impl > , DefaultIEWDefaultCommit< Impl > , DefaultRename< Impl > , DefaultRenameDefaultIEW< Impl > , ElasticTrace , FullO3CPU< Impl > , InstructionQueue< Impl > , IssueStruct< Impl > , LSQ< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , O3CPUImpl , ROB< Impl > , TimeBufStruct< Impl >