Here is a list of all class members with links to the classes they belong to:

- c -

• c : ArmISA::PMU , AtomicOpCAS< T > , Cycles , MathExpr::OpSearch
• C0 : MipsISA::PTE , PowerISA::PTE , RiscvISA::PTE
• c0_config : SparcISA::TLB
• c0_tsb_ps0 : SparcISA::TLB
• c0_tsb_ps1 : SparcISA::TLB
• C1 : MipsISA::PTE , PowerISA::PTE , RiscvISA::PTE
• c_reg : ConditionRegisterState
• cache : BasePrefetcher , BaseTags
• Cache() : Cache
• cache : Cache::CacheReqPacketQueue , Cache::CpuSidePort , Cache::MemSidePort , CacheBlkVisitorWrapper
• CACHE_BLOCK_ZERO : Request
• CACHE_RESPONDING : Packet
• cacheAsi : SparcISA::TLB
• cacheAvail() : CacheMemory , PerfectCacheMemory< ENTRY >
• CacheBlk() : CacheBlk
• CacheBlkIsDirtyVisitor() : CacheBlkIsDirtyVisitor
• CacheBlkPrintWrapper() : CacheBlkPrintWrapper
• cacheBlkSize : DefaultFetch< Impl >
• CacheBlkVisitor() : CacheBlkVisitor
• CacheBlkVisitorWrapper() : CacheBlkVisitorWrapper
• cacheBlocked : DefaultFetch< Impl > , LSQUnit< Impl >::LSQSenderState
• cacheBlockMask : AtomicSimpleCPU::AtomicCPUDPort , LSQUnit< Impl > , Minor::LSQ , TimingSimpleCPU::DcachePort
• cacheBlockSize() : DmaDevice
• cacheBoundaries : FALRU
• cachedDisassembly : StaticInst
• cachedLocations : SnoopFilter
• cachedMsrIntersection : X86KvmCPU
• cachedPC : PowerISA::PCDependentDisassembly
• cachedSymtab : PowerISA::PCDependentDisassembly
• cacheEntry : SparcISA::TLB
• CacheKey : X86ISA::Decoder
• cacheLines : MemFootprintProbe
• cacheLinesAll : MemFootprintProbe
• cacheLineSize() : ComputeUnit , PCIConfig , System
• cacheLineSizeLg2 : MemFootprintProbe
• cacheMask : FALRU
• CacheMasterPort() : BaseCache::CacheMasterPort
• CacheMemory() : CacheMemory
• cachePnt : IGbE::DescCache< T >
• cachePort : GarnetSyntheticTraffic
• cacheProbe() : CacheMemory , PerfectCacheMemory< ENTRY >
• CacheRecorder() : CacheRecorder
• CacheReqPacketQueue() : Cache::CacheReqPacketQueue
• cacheResponding() : Packet
• CacheSlavePort() : BaseCache::CacheSlavePort
• cacheSnoop : QueuedPrefetcher
• cacheState : SparcISA::TLB
• cacheStorePorts : LSQUnit< Impl >
• CacheType : IGbE::DescCache< T >
• cacheUnblocked() : DefaultIEW< Impl > , InstructionQueue< Impl >
• cacheValid : SparcISA::TLB
• cachingPage : UFSHostDevice::UFSSCSIDevice
• calc : StackDistProbe
• calcAddr() : HsailISA::Call
• calcEA() : BaseO3DynInst< Impl >
• calcFreeIQEntries() : DefaultRename< Impl >
• calcFreeLQEntries() : DefaultRename< Impl >
• calcFreeROBEntries() : DefaultRename< Impl >
• calcFreeSQEntries() : DefaultRename< Impl >
• calcIndex() : StoreSet
• calcLane() : AddrOperandBase , NoRegAddrOperand , RegAddrOperand< RegOperandType >
• calcLocHistIdx() : TournamentBP
• calcPacketTiming() : BaseXBar
• calcPciConfigAddr() : Malta , T1000
• calcPciIOAddr() : Malta , T1000
• calcPciMemAddr() : Malta , T1000
• calcReceiveTick() : DistIface::RecvScheduler
• calcResolution() : BaseKvmTimer , PerfKvmTimer , PosixKvmTimer
• calcSSID() : StoreSet
• calcStackDist() : StackDistCalc
• calcStackDistAndUpdate() : StackDistCalc
• calculatePrefetch() : QueuedPrefetcher , StridePrefetcher , TaggedPrefetcher
• calculateVC() : NetworkInterface
• calculateVectorIndex() : TimeBuffer< T >
• calcUniform() : NoRegAddrOperand , RegAddrOperand< RegOperandType >
• calcUniformBase() : AddrOperandBase
• calcVector() : AddrOperandBase , NoRegAddrOperand , RegAddrOperand< RegOperandType >
• Call() : HsailISA::Call
• CallArgMem() : CallArgMem
• callArgMem : Wavefront
• callArgs : ListOperand
• callback : DmaCallback::DmaChunkEvent
• callbackDataAvail : Uart , VirtIOConsole
• callbackKick : PciVirtIO
• CallbackQueue : Callback
• callbacks : CallbackQueue
• CallbackType : BasePixelPump::PixelEvent
• callpal() : AlphaISA::Kernel::Statistics
• callsys : PAL
• canAccept() : DRAMSim2Wrapper
• canAllocate() : PoolManager , SimplePoolManager
• cancel() : DmaReadFifo::DmaDoneEvent
• canceled() : DmaReadFifo::DmaDoneEvent
• canCoalesce() : TLBCoalescer
• CanCommit : BaseDynInst< Impl >
• canCommit() : ROB< Impl >
• canEarlyIssue : Minor::MinorDynInst
• canForwardDataToLoad() : Minor::LSQ::StoreBuffer
• canHandleInterrupts : DefaultCommit< Impl >
• canInsert() : Minor::FUPipeline , Minor::LSQ::StoreBuffer
• canInstIssue() : Minor::Scoreboard
• CanIssue : BaseDynInst< Impl >
• canPrefetch() : MSHRQueue
• canPushIntoStoreBuffer() : Minor::LSQ
• canRename() : UnifiedRenameMap
• canRequest() : Minor::LSQ
• canReserve() : LdsState , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , Minor::Reservable
• canSendToMemorySystem() : Minor::LSQ
• cantForwardFromFUIndices : Minor::FUPipeline , MinorFU
• canWB : LSQUnit< Impl >::SQEntry
• capabilities() : FuncUnit
• capabilityList : FuncUnit , FUPool , Minor::FUPipeline , MinorOpClassSet
• capabilityPtr : PCIConfig
• capacitors : ThermalModel
• capacity() : CircleBuf< T > , Fifo< T > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , VirtIOBlock::Config
• capacityLower : UFSHostDevice::UFSSCSIDevice
• capacityUpper : UFSHostDevice::UFSSCSIDevice
• capCoalescedMMIO() : Kvm
• capDebugRegs() : Kvm
• capExtendedCPUID() : Kvm
• capIRQChip() : Kvm
• caplen : pcap_pkthdr
• capNumMemSlots() : Kvm
• capOneReg() : Kvm
• capSetTSSAddress() : Kvm
• captureBitmap : VncInput
• captureCurrentFrame : VncInput
• captureEnabled : VncInput
• captureFrameBuffer() : VncInput
• captureLastHash : VncInput
• captureOutputDirectory : VncInput
• capUserMemory() : Kvm
• capUserNMI() : Kvm
• capVCPUEvents() : Kvm
• capXCRs() : Kvm
• capXSave() : Kvm
• cardbusCIS : PCIConfig
• cascadeBits : X86ISA::I8259
• cascadeMode : X86ISA::I8259
• cause : CountedExitEvent , GlobalSimLoopExitEvent , LocalSimLoopExitEvent , MipsISA::RemoteGDB::MipsGdbRegCache
• caux : ecoff_fdr
• cbAuxOffset : ecoff_symhdr
• cbDnOffset : ecoff_symhdr
• cbExtOffset : ecoff_symhdr
• cbFdOffset : ecoff_symhdr
• cbLine : ecoff_fdr , ecoff_symhdr
• cbLineOffset : ecoff_fdr , ecoff_symhdr , pdr
• cbOptOffset : ecoff_symhdr
• cbPdOffset : ecoff_symhdr
• CbrDirectInst() : HsailISA::CbrDirectInst
• cbRfdOffset : ecoff_symhdr
• CbrIndirectInst() : HsailISA::CbrIndirectInst
• CbrInstBase() : HsailISA::CbrInstBase< TargetType >
• cbSs : ecoff_fdr
• cbSsExtOffset : ecoff_symhdr
• cbSsOffset : ecoff_symhdr
• cbSymOffset : ecoff_symhdr
• cc() : Net::TcpOpt
• cchip : Malta , Tsunami
• ccList : UnifiedFreeList
• ccMap : UnifiedRenameMap
• ccreg : ArmISA::AnyReg
• CCReg : BaseO3DynInst< Impl > , ExecContext , PhysRegFile , SimpleExecContext , SimpleThread , ThreadContext
• ccReg : X86ISA::AnyReg
• ccRegFile : PhysRegFile
• ccRegfileReads : FullO3CPU< Impl >
• ccRegfileWrites : FullO3CPU< Impl >
• ccsr : dp_regs
• cdf : Stats::ScalarPrint
• ce : CopyEngine::CopyEngineChannel
• cedeSIMD() : ComputeUnit
• cePort : CopyEngine::CopyEngineChannel
• CfgCtrl : RealViewCtrl
• CfgData : RealViewCtrl
• CfgData1 : RealViewCtrl
• CfgData2 : RealViewCtrl
• CfgStat : RealViewCtrl
• cflush : PAL
• ch_b : PixelConverter
• ch_g : PixelConverter
• ch_r : PixelConverter
• chainRead() : VirtDescriptor
• chainSize() : VirtDescriptor
• chainWrite() : VirtDescriptor
• chan : CopyEngine
• chanCount : CopyEngineReg::Regs
• changeAddress() : Check
• changeConfig() : Sinic::Device
• changed : Trace::ArmNativeTrace::ThreadState
• changedPC : CheckerCPU
• changedROBEntries() : DefaultCommit< Impl >
• changedROBNumEntries : DefaultCommit< Impl >
• changeMode() : AlphaISA::Kernel::Statistics
• changePermission() : AbstractCacheEntry , AbstractEntry , PerfectCacheMemory< ENTRY >
• changeStream() : Minor::Fetch1
• Channel() : PixelConverter::Channel
• channelId : CopyEngine::CopyEngineChannel
• channelOrder : Brig::BrigOperandConstantImage
• channelRead() : CopyEngine::CopyEngineChannel
• channels : DRAMCtrl
• ChannelState : CopyEngine::CopyEngineChannel
• channelType : Brig::BrigOperandConstantImage
• channelWrite() : CopyEngine::CopyEngineChannel
• character : cp::Format
• characteristicExtBytes : X86ISA::SMBios::BiosInformation
• characteristics : X86ISA::SMBios::BiosInformation
• Check() : Check
• check() : FALRU , PacketFifo , Stats::Info , Stats::InfoAccess , Stats::InfoProxy< Stat, Base > , Stats::ProxyInfo , Stats::ValueBase< Derived > , Stats::Vector2dBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor > , Trace::ArmNativeTrace , Trace::NativeTrace , Trace::SparcNativeTrace , Trace::X86NativeTrace
• check_for_wakeup() : SwitchAllocator
• checkAddrSizeFaultAArch64() : ArmISA::TableWalker
• checkAdvSIMDOrFPEnabled32() : ArmISA::ArmStaticInst
• checkAndIssue() : TraceCPU::ElasticDataGen
• checkAndSchedExitEvent() : TraceCPU
• checkBpLen() : BaseRemoteGDB , X86ISA::RemoteGDB
• checkCacheability() : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• checkClear() : StoreSet
• checkCoherence() : GPUCoalescer , Sequencer
• checkCondition() : X86ISA::X86MicroopBase
• checkConflictingSnoop() : Cache::CacheReqPacketQueue
• checkDrain() : FlashDevice , IGbE , UFSHostDevice
• checkDrainDone() : DRAMCtrl::Rank
• checkELMatch() : ArmISA::TLB
• checkEmptyROB : DefaultCommit< Impl >
• checker : BaseSimpleCPU
• Checker() : Checker< Impl >
• checker : FullO3CPU< Impl >
• CheckerCPU() : CheckerCPU
• checkerCPU : CheckerThreadContext< TC >
• checkerTC : CheckerThreadContext< TC >
• CheckerThreadContext() : CheckerThreadContext< TC >
• checkExtension() : Kvm
• checkFlags() : CheckerCPU
• checkForDeadlock() : RubyDirectedTester , RubyTester
• checkForInterrupts() : BaseSimpleCPU
• CheckForPassword : X86ISA::I8042
• checkForStdio() : OutputDirectory
• checkFPAdvSIMDEnabled64() : ArmISA::ArmStaticInst
• checkFPAdvSIMDTrap64() : ArmISA::ArmStaticInst
• checkFunctional() : Bridge::BridgeMasterPort , MSHR , MSHR::TargetList , Packet , PacketQueue , Queue< Entry > , QueuedMasterPort , QueuedSlavePort , SerialLink::SerialLinkMasterPort , WriteQueueEntry , WriteQueueEntry::TargetList
• checkInst() : StoreSet
• checkInterrupt() : DefaultFetch< Impl >
• checkInterrupts() : AlphaISA::Interrupts , ArmISA::Interrupts , Minor::Execute , MipsISA::Interrupts , PowerISA::Interrupts , RiscvISA::Interrupts , SparcISA::Interrupts , X86ISA::Interrupts
• checkInterruptsRaw() : X86ISA::Interrupts
• checkLoads : LSQUnit< Impl >
• checkLockedAddrList() : AbstractMemory
• checkMisprediction() : DefaultIEW< Impl >
• checkName() : Label
• checkNetworkAllocation() : Network
• CheckPassword : X86ISA::I8042
• checkPcEventQueue() : BaseSimpleCPU
• checkPermissions() : ArmISA::TLB
• checkPermissions64() : ArmISA::TLB
• CheckpointIn() : CheckpointIn
• checkpointReschedule() : EventQueue
• checkPortCache() : BaseXBar
• checkProtocolVersion() : VncServer
• checkR11 : Trace::X86NativeTrace
• checkR11Reg() : Trace::X86NativeTrace
• checkRaw() : ArmISA::Interrupts
• checkRcx : Trace::X86NativeTrace
• checkRcxReg() : Trace::X86NativeTrace
• checkReg() : Trace::NativeTrace
• checkReschedule() : NetworkInterface
• checkResourceAvailable() : CacheMemory
• checkSecurity() : VncServer
• checkSignalsAndUpdate() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• checkSnoop() : LSQUnit< Impl >
• checkSoftInt() : SparcISA::ISA
• checkStall() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• checkStallQueue() : NetworkInterface
• checkStartEvent : RubyTester
• CheckStartEvent() : RubyTester::CheckStartEvent
• CheckTable() : CheckTable
• checkViolations() : LSQUnit< Impl >
• checkWfiWake() : ArmISA::Interrupts
• checkWrite() : CacheBlk
• checkXMM() : Trace::X86NativeTrace
• child : CowDiskImage
• childClearTID : Process
• ChildList : ProfileNode
• children : ClockDomain , ProfileNode
• chkInterrupt() : IGbE
• choiceCounters : BiModeBP
• choiceCtrBits : BiModeBP , TournamentBP
• choiceCtrs : TournamentBP
• choiceHistoryMask : BiModeBP , TournamentBP
• choicePredictorSize : BiModeBP , TournamentBP
• choiceThreshold : BiModeBP , TournamentBP
• chooseNext() : DRAMCtrl
• chooseWave() : OFSchedulingPolicy , RRSchedulingPolicy , Scheduler , SchedulingPolicy< Impl >
• chunk : LdsChunk
• chunkComplete() : DmaCallback
• ChunkGenerator() : ChunkGenerator
• chunkIdx : X86ISA::Decoder
• chunkMap : LdsState
• chunks : X86ISA::Decoder::InstBytes
• chunkSize : ChunkGenerator
• ci : LTAGE::BranchInfo
• CircleBuf() : CircleBuf< T >
• ckptCount : Serializable
• ckptMaxCount : Serializable
• ckptPrevCount : Serializable
• ckptRestore : DistIface::RecvScheduler
• cksum() : Net::TcpOpt
• classCode : PCIConfig
• ClassInst() : HsailISA::ClassInst< DataType >
• Clcd : RealViewCtrl
• ClcdCrsrClip : Pl111
• clcdCrsrClip : Pl111
• ClcdCrsrConfig : Pl111
• clcdCrsrConfig : Pl111
• ClcdCrsrCtrl : Pl111
• clcdCrsrCtrl : Pl111
• ClcdCrsrIcr : Pl111
• clcdCrsrIcr : Pl111
• ClcdCrsrImsc : Pl111
• clcdCrsrImsc : Pl111
• ClcdCrsrMis : Pl111
• clcdCrsrMis : Pl111
• ClcdCrsrPalette0 : Pl111
• clcdCrsrPalette0 : Pl111
• ClcdCrsrPalette1 : Pl111
• clcdCrsrPalette1 : Pl111
• ClcdCrsrRis : Pl111
• clcdCrsrRis : Pl111
• ClcdCrsrXY : Pl111
• clcdCrsrXY : Pl111
• ClcdSer : RealViewCtrl
• ClDriver() : ClDriver
• CleanEvict : MemCmd
• cleanEvictBlk() : Cache
• cleanup() : X86ISA::GpuTLB
• cleanupEvent : TLBCoalescer
• CleanupEvent() : TLBCoalescer::CleanupEvent
• cleanupEvent : X86ISA::GpuTLB
• cleanupQueue : TLBCoalescer , X86ISA::GpuTLB
• cleanupRefs() : BaseSetAssoc , BaseTags
• cleanUpRemovedInsts() : FullO3CPU< Impl >
• clear() : AbstractBloomFilter , AddrRangeMap< V > , AlphaISA::Interrupts , AlphaISA::ISA , AlphaISA::StackTrace , ArchTimer::Interrupt , ArmISA::Interrupts , ArmISA::ISA , ArmISA::StackTrace , BlockBloomFilter , BulkBloomFilter , CallbackQueue , cp::Format , DataBlock , EtherSwitch::Interface::PortFifo , Flags< T > , FrameBuffer , FunctionProfile , H3BloomFilter , Histogram , IntrControl , LSB_CountingBloomFilter , MessageBuffer , MipsISA::Interrupts , MipsISA::ISA , MipsISA::StackTrace , MultiBitSelBloomFilter , MultiGrainBloomFilter , NetDest , NonCountingBloomFilter , PacketFifo , PacketFifoEntry , PowerISA::Interrupts , PowerISA::ISA , PowerISA::StackTrace , ProfileNode , RiscvISA::Interrupts , RiscvISA::ISA , RiscvISA::StackTrace , Set , SparcISA::Interrupts , SparcISA::ISA , SparcISA::PageTableEntry , SparcISA::TlbMap , StoreSet , SymbolTable , Time , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement , Trie< Key, Value > , Trie< Key, Value >::Node , WriteMask , X86ISA::Interrupts , X86ISA::ISA , X86ISA::StackTrace
• clear64() : ArmISA::ISA
• clear_request_vector() : SwitchAllocator
• clearAll() : AlphaISA::Interrupts , ArmISA::Interrupts , MipsISA::Interrupts , PowerISA::Interrupts , RiscvISA::Interrupts , SparcISA::Interrupts , X86ISA::Interrupts
• clearArchRegs() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• clearBankedDistRange() : MuxingKvmGic
• clearBlockCached() : Packet
• clearBlocked() : BaseCache::CacheSlavePort , BaseCache
• clearCanCommit() : BaseDynInst< Impl >
• clearCanIssue() : BaseDynInst< Impl >
• clearConsoleInt() : Malta , Pc , Platform , RealView , T1000 , Tsunami
• clearDistRange() : MuxingKvmGic
• clearDownstreamPending() : MSHR , MSHR::TargetList
• clearDRIR() : TsunamiCChip
• clearFetchFault : DefaultFetchDefaultDecode< Impl >
• clearFlags() : Event
• clearFromParent() : TimingSimpleCPU::SplitFragmentSenderState
• clearInIQ() : BaseDynInst< Impl >
• clearInROB() : BaseDynInst< Impl >
• clearInst() : DependencyGraph< DynInstPtr >
• clearInstDests() : Minor::Scoreboard
• clearInt() : BaseGic , GenericPciHost , MuxingKvmGic , PciHost , PciHost::DeviceInterface , Pl390
• clearInterrupt : TimeBufStruct< Impl >::commitComm , UFSHostDevice
• clearInterrupts() : Pl011
• clearIntr() : MaltaCChip , MaltaIO
• clearIPI() : MaltaCChip , TsunamiCChip
• clearIssued() : BaseDynInst< Impl >
• clearITI() : MaltaCChip , TsunamiCChip
• clearLoadLocks() : CacheBlk
• clearLocked() : AbstractCacheEntry , CacheMemory
• clearLQ() : LSQUnit< Impl >
• clearMemBarrier() : Minor::LSQ
• clearNonunitEntry() : Prefetcher
• clearPciInt() : Malta , Pc , Platform , RealView , T1000 , Tsunami
• clearPeriod : StoreSet
• clearPIC() : TsunamiIO
• clearPortCache() : BaseXBar
• clearPPI() : KvmKernelGicV2
• clearPPInt() : BaseGic , MuxingKvmGic , Pl390
• clearReadSignal() : UFSHostDevice::UFSSCSIDevice
• clearRegArrayBit() : X86ISA::Interrupts
• clearRegDep() : TraceCPU::ElasticDataGen::GraphNode
• clearReservedSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• clearRobDep() : TraceCPU::ElasticDataGen::GraphNode
• clearSerializeAfter() : BaseDynInst< Impl >
• clearSerializeBefore() : BaseDynInst< Impl >
• clearSignal() : UFSHostDevice::UFSSCSIDevice
• clearSingleStep() : BaseRemoteGDB
• clearSPI() : KvmKernelGicV2
• clearSQ() : LSQUnit< Impl >
• clearStats() : AddressProfiler , MessageBuffer , PerfectSwitch , RubyDirectedTester , RubyTester , Throttle
• clearSummary() : StoreTrace
• clearTempBreakpoint() : BaseRemoteGDB
• clearTempStoreUntil() : ElasticTrace
• clearUnknownPages() : FlashDevice
• clearUsedBits() : SparcISA::TLB
• Client : ArmISA::TlbEntry
• ClientCutText : VncInput
• ClientFrameBufferUpdate : VncInput
• ClientKeyEvent : VncInput
• ClientMessages : VncInput
• ClientPointerEvent : VncInput
• ClientSetEncodings : VncInput
• ClientSetPixelFormat : VncInput
• cline : ecoff_fdr
• clk_in : Pl050
• clkdiv : Pl050
• clkPeriodAtPerfLevel() : DVFSHandler , SrcClockDomain
• clksel : Pl111
• Clobber : PageTableBase
• clock : Shader , Sp804::Timer , TLBCoalescer , X86ISA::GpuTLB
• Clock100 : RealViewCtrl
• Clock24 : RealViewCtrl
• clock_data : MC146818
• clock_remainder : ArmISA::PMU
• clock_t : ArmFreebsd32 , ArmFreebsd64 , ArmLinux32 , ArmLinux64 , FreeBSD , Linux
• clockDivider : DerivedClockDomain
• ClockDomain() : ClockDomain
• clockDomain : Clocked
• Clocked() : Clocked
• clocked_object : PowerModel , PowerModelState
• clockEdge() : Clocked
• ClockedObject() : ClockedObject
• ClockedObjectDumpCallback() : ClockedObjectDumpCallback
• ClockEvent : Ticked , Ticked::ClockEvent
• clockID : PosixKvmTimer
• clockPeriod() : ClockDomain , Clocked , DRAMSim2Wrapper , RealViewOsc , SrcClockDomain
• clocksLeft() : Intel8254Timer::Counter::CounterEvent
• clone() : DeviceFDEntry , FDEntry , FileFDEntry , Message , PipeFDEntry , Process , RubyRequest , X86ISA::I386LinuxProcess , X86ISA::I386Process , X86ISA::X86_64LinuxProcess , X86ISA::X86_64Process , X86ISA::X86Process
• close() : HexFile , OutputDirectory , RawDiskImage
• closeFDEntry() : FDArray
• closeStreams() : MemTraceProbe , Trace::InstPBTrace
• clrfen : PAL
• ClrImportant : Bitmap::InfoHeaderV1
• ClrUsed : Bitmap::InfoHeaderV1
• clusivity : Cache
• cmap : Stats::SparseHistData , Stats::SparseHistStor
• cmd : GdbCommand::Context , MemCmd , Packet , ProbePoints::PacketInfo , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement
• cmd_async_cont() : BaseRemoteGDB
• cmd_async_step() : BaseRemoteGDB
• cmd_byte : GdbCommand::Context
• cmd_clr_hw_bkpt() : BaseRemoteGDB
• cmd_cont() : BaseRemoteGDB
• cmd_detach() : BaseRemoteGDB
• cmd_mem_r() : BaseRemoteGDB
• cmd_mem_w() : BaseRemoteGDB
• cmd_query_var() : BaseRemoteGDB
• cmd_reg_r() : BaseRemoteGDB
• cmd_reg_w() : BaseRemoteGDB
• cmd_set_hw_bkpt() : BaseRemoteGDB
• cmd_set_thread() : BaseRemoteGDB
• cmd_signal() : BaseRemoteGDB
• cmd_step() : BaseRemoteGDB
• cmd_unsupported() : BaseRemoteGDB
• cmdBytes : IdeDisk
• cmdBytesLeft : IdeDisk
• cmdDisable() : HDLcd
• cmdEnable() : HDLcd
• CmdError() : BaseRemoteGDB::CmdError
• cmdline() : AtagCmdline
• cmdList : DRAMCtrl::Rank
• cmdReg : IdeDisk
• cmdString() : Packet
• cmdsts : ns_desc32 , ns_desc64
• cmdSyncAck : DistHeaderPkt
• cmdSyncReq : DistHeaderPkt
• cmdToIndex() : Packet
• CMDUCMDARG1 : UFSHostDevice::HCIMem
• CMDUCMDARG2 : UFSHostDevice::HCIMem
• CMDUCMDARG3 : UFSHostDevice::HCIMem
• CMDUICCMDR : UFSHostDevice::HCIMem
• cmos : SouthBridge
• Cmos() : X86ISA::Cmos
• CmovInst() : HsailISA::CmovInst< DataType >
• cmpAndSwap() : Cache
• CmpInst() : HsailISA::CmpInst< DestDataType, SrcDataType >
• CmpInstBase() : HsailISA::CmpInstBase< DestOperandType, SrcOperandType >
• cmpMask() : WriteMask
• cmpOp : HsailISA::CmpInstBase< DestOperandType, SrcOperandType >
• cnt() : LinearEquation
• co : ClockedObjectDumpCallback
• coalescedAccesses : TLBCoalescer
• coalescedReq : TLBCoalescer
• coalescedRxDesc : EtherDevice
• coalescedRxIdle : EtherDevice
• coalescedRxOk : EtherDevice
• coalescedRxOrn : EtherDevice
• coalescedSwi : EtherDevice
• coalescedTotal : EtherDevice
• coalescedTxDesc : EtherDevice
• coalescedTxIdle : EtherDevice
• coalescedTxOk : EtherDevice
• coalesceMMIO() : KvmVM
• coalescer : TLBCoalescer::CleanupEvent , TLBCoalescer::CpuSidePort , TLBCoalescer::IssueProbeEvent , TLBCoalescer::MemSidePort
• coalescerFIFO : TLBCoalescer
• coalescerToVrfBusWidth : ComputeUnit
• CoalescingFIFO : TLBCoalescer
• CoalescingTable : GPUCoalescer , TLBCoalescer
• coalescingWindow : TLBCoalescer
• cobol_main : ecoff_extsym
• code : EmbeddedPython , GlobalSimLoopExitEvent , LocalSimLoopExitEvent , MipsISA::AddressErrorFault , MipsISA::MipsFault< T > , MipsISA::MipsFaultBase , MipsISA::MipsFaultBase::FaultVals , MipsISA::TlbFault< T > , MipsISA::TlbModifiedFault
• code_offs : HsaKernelInfo
• code_ptr : HsaQueueEntry
• code_size : HsaDriverSizes
• codeFiles : ClDriver
• codeOffToKernelName() : ClDriver
• CodeSectionIndex : BrigObject
• CoherentXBar() : CoherentXBar
• CoherentXBarMasterPort() : CoherentXBar::CoherentXBarMasterPort
• CoherentXBarSlavePort() : CoherentXBar::CoherentXBarSlavePort
• coissue_return : Shader
• colAllowedAt : DRAMCtrl::Bank
• collateStats() : AbstractController , AddressProfiler , GarnetNetwork , GPUCoalescer , Network , PerfectSwitch , Profiler , Router , RubySystem , Sequencer , SimpleNetwork , Switch , Throttle
• collective : DistHeaderPkt
• collectStatistics() : ExecStage , ScoreboardCheckStage
• cols : VirtIOConsole::Config
• column : Brig::BrigDirectiveLoc
• columnsPerRowBuffer : DRAMCtrl
• columnsPerStripe : DRAMCtrl
• command : CommandReg , CopyEngineReg::ChanRegs , CopyEngineReg::DmaDesc , dp_regs
• Command() : DRAMCtrl::Command , HDLcd
• command : HDLcd
• Command : MemCmd , Packet
• command : PCIConfig
• Command : Sinic::Device
• command() : Sinic::Device
• Command : X86ISA::I8042 , X86ISA::PS2Keyboard , X86ISA::PS2Mouse
• command_map : BaseRemoteGDB
• commandByte : X86ISA::I8042
• commandDescBaseAddrHi : UFSHostDevice::UTPTransferReqDesc
• commandDescBaseAddrLo : UFSHostDevice::UTPTransferReqDesc
• commandHandler() : UFSHostDevice
• commandInfo : MemCmd
• commandLast : X86ISA::I8042
• CommandLine() : LinuxAlphaSystem , LinuxMipsSystem
• commandLine : LinuxX86System
• CommandLineSize : BareIronMipsSystem , LinuxAlphaSystem , LinuxMipsSystem
• commandPort : X86ISA::I8042
• commandUPIU : UFSHostDevice::UTPTransferCMDDesc
• commit() : DefaultCommit< Impl > , DefaultCommit< Impl >::TrapEvent
• Commit : DefaultRename< Impl >
• commit : DefaultRename< Impl >::Stalls , ElasticTrace::TraceInfo , FullO3CPU< Impl > , IndirectPredictor , InstructionQueue< Impl > , Minor::Execute
• Commit : SimpleCPUPolicy< Impl >
• commit_ptr : DefaultRename< Impl >
• commitDrained() : FullO3CPU< Impl >
• commitEligibleSamples : DefaultCommit< Impl >
• commitHead() : DefaultCommit< Impl >
• CommitIdx : FullO3CPU< Impl >
• commitInfo : TimeBufStruct< Impl >
• commitInst() : Minor::Execute
• commitInsts() : DefaultCommit< Impl >
• commitLimit : Minor::Execute
• commitLoad() : LSQUnit< Impl >
• commitLoads() : LSQ< Impl > , LSQUnit< Impl >
• commitNonSpecStalls : DefaultCommit< Impl >
• CommitPolicy : DefaultCommit< Impl >
• commitPolicy : DefaultCommit< Impl >
• commitPriority : Minor::Execute
• commitRenameMap : FullO3CPU< Impl >
• commitSquashedInsts : DefaultCommit< Impl >
• commitStatus : DefaultCommit< Impl >
• CommitStatus : DefaultCommit< Impl >
• commitStores() : LSQ< Impl > , LSQUnit< Impl >
• Committed : BaseDynInst< Impl >
• committed : LSQUnit< Impl >::SQEntry
• committedInsts : FullO3CPU< Impl >
• committedInstType : Minor::MinorStats
• committedOps : FullO3CPU< Impl >
• committedStores : DefaultCommit< Impl >
• commitTick : ElasticTrace::TraceInfo
• commitToDecodeDelay : DefaultDecode< Impl >
• commitToFetchDelay : DefaultFetch< Impl >
• commitToIEWDelay : DefaultCommit< Impl > , DefaultIEW< Impl > , InstructionQueue< Impl >
• commitToRenameDelay : DefaultRename< Impl >
• commitWidth : DefaultCommit< Impl > , DefaultRename< Impl >
• CommMonitor() : CommMonitor
• CommMonitorSenderState() : CommMonitor::CommMonitorSenderState
• CommonInstBase() : HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands >
• commPage : ArmFreebsdProcess32 , ArmLinuxProcess32
• comp : LTAGE::FoldedHistory
• compare : Brig::BrigInstCmp , ThreadContext
• compareValue() : ArchTimer
• CompatAddrSpaceMod() : X86ISA::IntelMP::CompatAddrSpaceMod
• compDelay : ElasticTrace::TraceInfo , TraceCPU::ElasticDataGen::GraphNode
• compDelayPhysRegDep() : ElasticTrace
• compDelayRob() : ElasticTrace
• compLength : LTAGE::FoldedHistory
• complete : ArmISA::Stage2LookUp , ChunkGenerator , LSQUnit< Impl >::LSQSenderState , MemChecker::Transaction , MemChecker::WriteCluster
• Complete : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• completeAcc() : BaseO3DynInst< Impl > , GPUDynInst , GPUStaticInst , HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , StaticInst
• completeBarrier() : MemDepUnit< MemDepPred, Impl >
• COMPLETED : ArmISA::TableWalker
• Completed : BaseDynInst< Impl >
• completed : LSQUnit< Impl >::SQEntry , MemDepUnit< MemDepPred, Impl > , MemDepUnit< MemDepPred, Impl >::MemDepEntry
• completeDataAccess() : LSQUnit< Impl > , TimingSimpleCPU
• completeDrain() : ArmISA::TableWalker
• completedWfs : ComputeUnit
• completeHitCallback() : GPUCoalescer
• completeIfetch() : TimingSimpleCPU
• completeIssue() : GPUCoalescer
• completeMax : MemChecker::WriteCluster
• completeMemAccess() : TraceCPU::ElasticDataGen
• completeMemBarrierInst() : Minor::LSQ
• completeMemInst() : InstructionQueue< Impl >
• completeRead() : MemChecker::ByteTracker , MemChecker
• completeRequest() : GarnetSyntheticTraffic , GlobalMemPipeline , MemTest
• completeStore() : LSQUnit< Impl >
• completeWrite() : MemChecker::ByteTracker , MemChecker , MemChecker::WriteCluster
• completionAddr : CopyEngineReg::ChanRegs
• completionAddress : IGbE::TxDescCache
• completionDataReg : CopyEngine::CopyEngineChannel
• completionEnabled : IGbE::TxDescCache
• completionEvent : DmaPort::DmaReqState
• CompletionWrite : CopyEngine::CopyEngineChannel
• completionWriteback() : IGbE::TxDescCache
• CompoundFlag() : Debug::CompoundFlag
• Compression : Bitmap::InfoHeaderV1
• computeActualWgSz() : Wavefront
• computeIndices : LTAGE::ThreadHistory
• computeStats() : BaseSetAssoc , BaseTags , ClockedObject , DRAMCtrl::Rank
• computeTags : LTAGE::ThreadHistory
• computeUnit : AtomicOpCAS< T >
• ComputeUnit() : ComputeUnit
• computeUnit : ComputeUnit::CUExitCallback , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , ConditionRegisterState , ExecStage , FetchStage , FetchUnit , GlobalMemPipeline , GPUExecContext , LocalMemPipeline , ScheduleStage , ScoreboardCheckStage , VecRegisterState , VectorRegisterFile , Wavefront
• cond : ArmISA::FpRegRegRegCondOp , HsailISA::CbrInstBase< TargetType > , TimingExprIf
• condBranch : LTAGE::BranchInfo
• condCode : ArmISA::BranchImmCond64 , ArmISA::DataXCondCompImmOp , ArmISA::DataXCondCompRegOp , ArmISA::DataXCondSelOp , ArmISA::FpCondCompRegOp , ArmISA::FpCondSelOp , ArmISA::PredOp
• condIncorrect : BPredUnit
• conditionalSquash() : O3ThreadContext< class >
• ConditionRegisterState() : ConditionRegisterState
• CondLogicOp() : PowerISA::CondLogicOp
• CondMoveOp() : PowerISA::CondMoveOp
• condOk() : PowerISA::BranchCond
• condPredicted : BPredUnit
• condRegState : Wavefront
• conf_record_buff_per_vc : FaultModel
• conf_record_first_fault_type : FaultModel
• conf_record_format : FaultModel
• conf_record_last_fault_type : FaultModel
• conf_record_vcs : FaultModel
• confBase : GenericPciHost
• confDeviceBits : GenericPciHost
• confidence : LTAGE::LoopEntry , StridePrefetcher::StrideEntry
• Config : A9SCU
• config : dp_regs , PciDevice
• Config : Sinic::Device
• config : VirtIO9PBase , VirtIOBlock , VirtIOConsole
• configAddress : X86ISA::GpuTLB , X86ISA::TLB
• configCP() : MipsISA::ISA
• configDelay : PciDevice
• configFile : CxxConfigManager , TrafficGen
• configManager : CxxConfigManager::SimObjectResolver
• configSize : VirtIODeviceBase
• ConfigTable() : X86ISA::IntelMP::ConfigTable
• configurations : FaultModel
• conflictingLoads : MemDepUnit< MemDepPred, Impl >
• conflictingStores : MemDepUnit< MemDepPred, Impl >
• confSize : GenericPciHost
• confTableReported : AbstractMemory , BackingStoreEntry
• connect() : TCPIface
• connectBasicBlocks() : ControlFlowInfo
• ConnectionState : VncServer
• connectMemPorts() : CheckerThreadContext< TC >
• connectSocket() : VirtIO9PSocket
• console : AlphaISA::StackTrace , AlphaSystem , MipsISA::StackTrace , MipsSystem , PowerISA::StackTrace , RiscvISA::StackTrace , RiscvSystem , X86ISA::StackTrace
• console_in() : Terminal
• consoleData : AlphaBackdoor
• consolePanicEvent : AlphaSystem , MipsSystem , RiscvSystem
• consoleSymtab : AlphaSystem , MipsSystem , RiscvSystem
• const_iterator : AddrRangeMap< V > , PacketFifo , PCEventQueue , QueuedPrefetcher
• const_range_t : PCEventQueue
• ConstNode() : Stats::ConstNode< T >
• constUDelaySkipEvent : FreebsdArmSystem , LinuxArmSystem
• ConstVectorNode() : Stats::ConstVectorNode< T >
• consume() : FunctionProfile
• consumeByte() : X86ISA::Decoder
• consumeBytes() : ArmISA::Decoder , X86ISA::Decoder
• consumeDescriptor() : VirtQueue
• consumeLink() : NetworkLink
• Consumer() : Consumer
• ConsumerEvent() : Consumer::ConsumerEvent
• consumerInst : DefaultIEW< Impl >
• cont : cp::Print
• ContainerPrint() : m5::stl_helpers::ContainerPrint< T >
• contains() : AddrRange
• containsAddrRangeOf() : Minor::LSQ::LSQRequest
• context() : AlphaISA::Kernel::Statistics , BaseRemoteGDB
• contextId() : BaseDynInst< Impl > , CacheBlk::Lock , CheckerThreadContext< TC > , LockedAddr , Minor::ExecContext , O3ThreadContext< class > , ProxyThreadContext< TC > , Request , SparcISA::TlbRange , ThreadContext , ThreadState
• contextIds : Process
• contextIdToVCpuId() : KvmVM
• ContextType : SparcISA::TLB
• contiguousHint() : ArmISA::TableWalker::LongDescriptor
• continued : TIR
• continueProcessing() : CopyEngine::CopyEngineChannel
• ContinuousPollHigh : X86ISA::I8042
• ContinuousPollLow : X86ISA::I8042
• Control : A9SCU
• control() : ArchTimer , Brig::BrigDirectiveControl , Pl011 , Sp804::Timer
• controlFlowDivergenceDist : ComputeUnit
• ControlFlowInfo() : ControlFlowInfo
• controller : AbstractController::MemoryPort
• controlPage : UFSHostDevice::UFSSCSIDevice
• ControlReg : PL031 , Sp804::Timer
• conv : HDLcd
• converter : Pl111
• convertLlToRead() : Packet
• convertScToWrite() : Packet
• coord : Brig::BrigOperandConstantSampler
• coordType : Brig::BrigInstImage
• copiesProcessed : CopyEngine
• CoprocessorUnusableFault() : MipsISA::CoprocessorUnusableFault
• coProcID : MipsISA::CoprocessorUnusableFault
• copt : ecoff_fdr
• copy() : PollQueue , RefCountingPtr< T >
• COPY_FLAGS : Packet
• copyArchRegs() : CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , SimpleThread , ThreadContext
• copyBankedDistRange() : MuxingKvmGic
• copyBuffer : CopyEngine::CopyEngineChannel
• copyCpuRegister() : MuxingKvmGic
• copyDistRange() : MuxingKvmGic
• copyDistRegister() : MuxingKvmGic
• CopyEngine() : CopyEngine
• CopyEngineChannel() : CopyEngine::CopyEngineChannel
• copyError() : Packet
• copyGicState() : MuxingKvmGic
• copyIn() : BaseBufferArg , FrameBuffer
• copyOut() : AtagHeader , BaseBufferArg , FrameBuffer
• copyout() : PacketFifo
• copypal : PAL
• copyPartial() : DataBlock
• copyResult() : Checker< Impl >
• copyState() : SimpleThread
• coreId() : Sequencer
• CoreSpecific() : MipsISA::CoreSpecific
• CoreTimers() : GenericTimer::CoreTimers
• CorrectlyPredictedBranch : Minor::BranchData
• count : ArmISA::ArmFault::FaultVals , AUXU , DmaCallback , InstructionQueue< Impl > , NetDest , ProfileNode , RefCounted , Set , SimPoint::BBInfo , SparcISA::SparcFaultBase::FaultVals
• countBankConflicts() : LdsState
• countCycles() : Minor::Pipeline , Ticked
• CountedExitEvent() : CountedExitEvent
• counter : Intel8254Timer
• Counter() : Intel8254Timer::Counter , Intel8254Timer::Counter::CounterEvent
• counter : Intel8254Timer::Counter::CounterEvent , SatCounter
• counterAtZero() : Sp804::Timer
• CounterEvent() : Intel8254Timer::Counter::CounterEvent
• counterInterrupt() : Intel8254Timer , X86ISA::I8254 , X86ISA::I8254::X86Intel8254Timer
• counterLimitReached() : ArchTimer
• counterMatch() : PL031
• counters : ArmISA::PMU
• CounterState() : ArmISA::PMU::CounterState
• countInst() : BaseSimpleCPU
• countInsts() : InstructionQueue< Impl > , ROB< Impl >
• countInt : UFSHostDevice
• countIssuedStore() : Minor::LSQ::StoreBuffer
• countNumSeqPkts : DramGen
• countPacketsAfter() : PacketFifo
• countPacketsBefore() : PacketFifo
• countPages : ComputeUnit
• countReadStarvingForAddress() : PersistentTable
• countStarvingForAddress() : PersistentTable
• countStat() : AlphaISA::AlignmentFault , AlphaISA::AlphaFault , AlphaISA::ArithmeticFault , AlphaISA::DtbAcvFault , AlphaISA::DtbAlignmentFault , AlphaISA::DtbFault , AlphaISA::DtbPageFault , AlphaISA::FloatEnableFault , AlphaISA::IntegerOverflowFault , AlphaISA::InterruptFault , AlphaISA::ItbAcvFault , AlphaISA::ItbFault , AlphaISA::ItbPageFault , AlphaISA::MachineCheckFault , AlphaISA::NDtbMissFault , AlphaISA::PalFault , AlphaISA::PDtbMissFault , AlphaISA::ResetFault , AlphaISA::UnimplementedOpcodeFault , ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , SparcISA::SparcFault< T > , SparcISA::SparcFaultBase
• CowDiskCallback() : CowDiskCallback
• CowDiskImage() : CowDiskImage
• cp() : SparcISA::PageTableEntry
• CP0 : MipsISA::ISA
• cp0 : MipsISA::ISA::CP0Event
• CP0_Config : MipsISA::CoreSpecific
• CP0_Config1 : MipsISA::CoreSpecific
• CP0_Config1_C2 : MipsISA::CoreSpecific
• CP0_Config1_CA : MipsISA::CoreSpecific
• CP0_Config1_DA : MipsISA::CoreSpecific
• CP0_Config1_DL : MipsISA::CoreSpecific
• CP0_Config1_DS : MipsISA::CoreSpecific
• CP0_Config1_EP : MipsISA::CoreSpecific
• CP0_Config1_FP : MipsISA::CoreSpecific
• CP0_Config1_IA : MipsISA::CoreSpecific
• CP0_Config1_IL : MipsISA::CoreSpecific
• CP0_Config1_IS : MipsISA::CoreSpecific
• CP0_Config1_M : MipsISA::CoreSpecific
• CP0_Config1_MD : MipsISA::CoreSpecific
• CP0_Config1_MMU : MipsISA::CoreSpecific
• CP0_Config1_PC : MipsISA::CoreSpecific
• CP0_Config1_WR : MipsISA::CoreSpecific
• CP0_Config2 : MipsISA::CoreSpecific
• CP0_Config2_M : MipsISA::CoreSpecific
• CP0_Config2_SA : MipsISA::CoreSpecific
• CP0_Config2_SL : MipsISA::CoreSpecific
• CP0_Config2_SS : MipsISA::CoreSpecific
• CP0_Config2_SU : MipsISA::CoreSpecific
• CP0_Config2_TA : MipsISA::CoreSpecific
• CP0_Config2_TL : MipsISA::CoreSpecific
• CP0_Config2_TS : MipsISA::CoreSpecific
• CP0_Config2_TU : MipsISA::CoreSpecific
• CP0_Config3 : MipsISA::CoreSpecific
• CP0_Config3_DSPP : MipsISA::CoreSpecific
• CP0_Config3_LPA : MipsISA::CoreSpecific
• CP0_Config3_M : MipsISA::CoreSpecific
• CP0_Config3_MT : MipsISA::CoreSpecific
• CP0_Config3_SM : MipsISA::CoreSpecific
• CP0_Config3_SP : MipsISA::CoreSpecific
• CP0_Config3_TL : MipsISA::CoreSpecific
• CP0_Config3_VEIC : MipsISA::CoreSpecific
• CP0_Config3_VInt : MipsISA::CoreSpecific
• CP0_Config_AR : MipsISA::CoreSpecific
• CP0_Config_AT : MipsISA::CoreSpecific
• CP0_Config_BE : MipsISA::CoreSpecific
• CP0_Config_MT : MipsISA::CoreSpecific
• CP0_Config_VI : MipsISA::CoreSpecific
• CP0_EBase_CPUNum : MipsISA::CoreSpecific
• CP0_IntCtl_IPPCI : MipsISA::CoreSpecific
• CP0_IntCtl_IPTI : MipsISA::CoreSpecific
• CP0_PerfCtr_M : MipsISA::CoreSpecific
• CP0_PerfCtr_W : MipsISA::CoreSpecific
• CP0_PRId : MipsISA::CoreSpecific
• CP0_PRId_CompanyID : MipsISA::CoreSpecific
• CP0_PRId_CompanyOptions : MipsISA::CoreSpecific
• CP0_PRId_ProcessorID : MipsISA::CoreSpecific
• CP0_PRId_Revision : MipsISA::CoreSpecific
• CP0_SrsCtl_HSS : MipsISA::CoreSpecific
• CP0_WatchHi_M : MipsISA::CoreSpecific
• CP0Event() : MipsISA::ISA::CP0Event
• cp0EventRemoveList : MipsISA::ISA
• cp0EventType : MipsISA::ISA::CP0Event
• CP0EventType : MipsISA::ISA
• cp0Updated : MipsISA::ISA
• CP_LdMiss : GPUCoalescer
• cp_seq : Trace::InstRecord
• cp_seq_valid : Trace::InstRecord
• CP_StMiss : GPUCoalescer
• CP_TCCLdHits : GPUCoalescer
• CP_TCCStHits : GPUCoalescer
• CP_TCPLdHits : GPUCoalescer
• CP_TCPLdTransfers : GPUCoalescer
• CP_TCPStHits : GPUCoalescer
• CP_TCPStTransfers : GPUCoalescer
• cpa : AnnotateDumpCallback , CPA , IGbE
• CPBR : VGic
• cpd : ecoff_fdr
• cpi : FullO3CPU< Impl > , Minor::MinorStats , TraceCPU
• cpl : Pl111
• cpsr : ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ArmISA::TableWalker::WalkerState , ArmISA::TLB
• cpsrWriteByInstr() : ArmISA::ArmStaticInst
• cptDir : CheckpointIn
• cpu : AlphaBackdoor , AlphaISA::Interrupts , ArmISA::Interrupts , AtomicSimpleCPU::AtomicCPUDPort , AtomicSimpleCPU::TickEvent , BaseDynInst< Impl > , BaseKvmCPU::KVMCpuPort , BaseKvmCPU::TickEvent , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , ElasticTrace , FullO3CPU< Impl >::DcachePort , FullO3CPU< Impl >::TickEvent , GarnetSyntheticTraffic::TickEvent , GenericTimerISA , GpuDispatcher , InstructionQueue< Impl > , Iob::IntMan , LSQ< Impl > , LSQUnit< Impl > , Minor::Decode , Minor::ExecContext , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , Minor::LSQ , Minor::Pipeline , MinorCPU::MinorCPUPort , MipsISA::ISA::CP0Event , O3ThreadContext< class > , O3ThreadState< class > , Pl390::PostIntEvent , PowerISA::Interrupts , RiscvISA::Interrupts , ROB< Impl > , SimpleExecContext , SparcISA::Interrupts , TimingSimpleCPU::FetchTranslation , TimingSimpleCPU::IprEvent , TimingSimpleCPU::TimingCPUPort , TimingSimpleCPU::TimingCPUPort::TickEvent , VGic::PostVIntEvent , X86ISA::Interrupts
• cpu_id : Pl390
• cpu_list : Pl390
• CPU_MAX : CpuLocalTimer , Pl390
• cpu_mondo_head : SparcISA::ISA
• cpu_mondo_tail : SparcISA::ISA
• CPU_SIZE : Pl390
• CPU_Switch_Pri : EventBase
• CPU_Tick_Pri : EventBase
• cpuBpr : Pl390
• cpuClearInt() : IGbE
• cpuClock : AlphaAccess , MipsAccess
• cpuEnabled : Pl390
• CpuEvent() : CpuEvent
• CpuEventList : CpuEvent
• cpuEventList : CpuEvent
• CpuEventWrapper() : CpuEventWrapper< T, F >
• cpuFlags : X86ISA::IntelMP::Processor
• cpuHighestInt : Pl390
• cpuId() : BaseDynInst< Impl > , CheckerThreadContext< TC > , O3ThreadContext< class > , ProxyThreadContext< TC > , ThreadContext , ThreadState
• CpuID : VGic
• CpuidResult() : X86ISA::CpuidResult
• cpuInterrupt() : NSGigE , Sinic::Base
• cpuIntrAck() : NSGigE , Sinic::Base
• cpuIntrClear() : NSGigE , Sinic::Base
• cpuIntrEnable : Sinic::Base
• cpuIntrPending() : NSGigE , Sinic::Base
• cpuIntrPost() : NSGigE , Sinic::Base
• CpuLocalTimer() : CpuLocalTimer , CpuLocalTimer::Timer
• cpuNum : CpuLocalTimer::Timer
• cpuPendingIntr : NSGigE , Sinic::Base
• cpuPioDelay : Pl390
• cpuPointer : Shader
• CPUPol : DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , O3CPUImpl
• CPUPolicy : FullO3CPU< Impl >
• CpuPort() : GarnetSyntheticTraffic::CpuPort , MemTest::CpuPort , RubyDirectedTester::CpuPort , RubyTester::CpuPort
• CpuPortIter : RubyPort
• cpuPostInt() : IGbE
• cpuPpiActive : Pl390
• cpuPpiPending : Pl390
• cpuPriority : Pl390
• cpuRange : KvmKernelGicV2 , Pl390
• cpuSgiActive : Pl390
• cpuSgiActiveExt : Pl390
• cpuSgiPending : Pl390
• cpuSgiPendingExt : Pl390
• cpuSidePort : BaseCache
• CpuSidePort() : Cache::CpuSidePort
• cpuSidePort : TLBCoalescer
• CpuSidePort() : TLBCoalescer::CpuSidePort
• cpuSidePort : X86ISA::GpuTLB
• CpuSidePort() : X86ISA::GpuTLB::CpuSidePort
• cpuSignature : X86ISA::IntelMP::Processor
• cpuStack : AlphaAccess , MipsAccess
• CPUStageId : Minor::Pipeline
• cpuStartup() : KvmVM
• cpuTarget : Pl390
• cpuThread : Shader
• CPUType : O3CPUImpl
• cpuWaitList : FullO3CPU< Impl >
• cr : CopyEngine::CopyEngineChannel , PowerISA::RemoteGDB::PowerGdbRegCache
• CRDD : NSGigE
• create() : ArmISA::PMU::EventType , Kvm , OutputDirectory
• createBackingStore() : PhysicalMemory
• createBasicBlocks() : ControlFlowInfo
• createDevice() : KvmVM
• createDmaEngine() : HDLcd
• createForUnserialize() : LocalSimLoopExitEvent
• createHsaObject() : HsaObject
• createIRQChip() : KvmVM
• createLinks() : Topology
• createMissPacket() : Cache
• createRead() : Packet
• createStreams() : ProtoInputStream
• createSubdirectory() : OutputDirectory
• createTimers() : GenericTimer
• createTraceFile() : Trace::InstPBTrace
• createVCPU() : KvmVM
• createVM() : Kvm
• createWrite() : Packet
• creatorID : X86ISA::ACPI::SysDescTable
• creatorRevision : X86ISA::ACPI::SysDescTable
• Credit() : Credit
• credit_conservation__credit_generation : FaultModel
• credit_conservation__credit_loss : FaultModel
• CreditLink() : CreditLink
• creditQueue : InputUnit
• cRegCount : HsaKernelInfo , HsaQueueEntry
• crfd : ecoff_fdr , ecoff_symhdr
• CrossbarSwitch() : CrossbarSwitch
• CrsrImage : Pl111
• CrsrImageSize : Pl111
• cs : X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache
• cserve : PAL
• csr : RiscvISA::RemoteGDB::RiscvGdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache
• csr_base : RiscvISA::RemoteGDB::RiscvGdbRegCache
• csum : iGbReg::RxDesc
• cSwap() : ArmISA::ArmStaticInst
• csym : ecoff_fdr
• ct0 : LTAGE::BranchInfo
• ct1 : LTAGE::BranchInfo
• CTDD : NSGigE
• ctr : AbstractController::StatsCallback , LTAGE::TageEntry , Network::StatsCallback , PowerISA::RemoteGDB::PowerGdbRegCache
• ctrInsts : BaseKvmCPU
• ctrl : CopyEngineReg::ChanRegs , IdeDisk , iGbReg::Regs
• ctrl32 : FXSave
• ctrl64 : FXSave
• CTRL_CNTACR_BASE : GenericTimerMem
• CTRL_CNTFRQ : GenericTimerMem
• CTRL_CNTNSAR : GenericTimerMem
• CTRL_CNTTIDR : GenericTimerMem
• CTRL_CNTVOFF_HI_BASE : GenericTimerMem
• CTRL_CNTVOFF_LO_BASE : GenericTimerMem
• ctrl_ext : iGbReg::Regs
• ctrlOffset : IdeController
• ctrlRange : GenericTimerMem
• ctrlRead() : GenericTimerMem
• ctrlreg : AlphaISA::AnyReg , ArmISA::AnyReg , MipsISA::AnyReg , PowerISA::AnyReg , SparcISA::AnyReg
• ctrlReg : X86ISA::AnyReg
• ctrlWrite() : GenericTimerMem
• ctrOk() : PowerISA::BranchCond
• ctrUpdate() : LTAGE
• CType : HsailISA::HsailDataType< _OperandType, _CType, _memType, _vgprType, IsBits >
• cu : GPUExecContext
• cu_id : ComputeUnit , GPUDynInst
• cuExitCallback : ComputeUnit
• CUExitCallback() : ComputeUnit::CUExitCallback
• cuList : Shader
• cuPort : LdsState
• curAddr : ChunkGenerator , Pl111
• curCid : NDRange
• curCycle() : Clocked , Shader , TLBCoalescer , X86ISA::GpuTLB
• curDmaDesc : CopyEngine::CopyEngineChannel
• curDoorbell : UFSHostDevice::UFSHostDeviceStats
• curFetching : IGbE::DescCache< T >
• curMacroStaticInst : BaseSimpleCPU , CheckerCPU
• curMsg : Trace::InstPBTrace
• curPrd : IdeDisk
• curPrdAddr : IdeDisk
• curPrefix() : Packet::PrintReqState
• curPrefixPtr : Packet::PrintReqState
• currBit : I2CBus
• currElement : TraceCPU::FixedRetryGen , TraceGen
• currELHOffset : ArmISA::ArmFault::FaultVals
• currELTOffset : ArmISA::ArmFault::FaultVals
• current : Stats::AvgStor , Trace::ArmNativeTrace::ThreadState
• currentBBV : SimPoint
• currentBBVInstCount : SimPoint
• currentClock : ClockDomain
• currentCode : BrigObject
• currentCount() : Intel8254Timer::Counter
• currentDirectory : CheckpointIn
• CurrentGlobalsOffset : SparcISA::ISA
• currentIter : LTAGE::BranchInfo , LTAGE::LoopEntry
• currentIterSpec : LTAGE::LoopEntry
• currentReadSSDQueue : UFSHostDevice::UFSHostDeviceStats
• CurrentReg : Sp804::Timer
• currentSCSIQueue : UFSHostDevice::UFSHostDeviceStats
• currentSection() : Serializable
• currentTemp : ThermalDomain
• currentTemperature() : ThermalDomain
• currentVoltage : VoltageDomain
• CurrentWindowOffset : SparcISA::ISA
• currentWriteSSDQueue : UFSHostDevice::UFSHostDeviceStats
• currState : ArmISA::TableWalker , TrafficGen
• currStates : X86ISA::Walker
• curSector : IdeDisk , MmDisk
• curSize : ChunkGenerator
• cursorImage : Pl111
• curState : VncServer
• curStaticInst : BaseSimpleCPU , CheckerCPU
• curTask : GpuDispatcher
• curTaskInfo() : Linux::ThreadInfo
• curTaskMm() : Linux::ThreadInfo
• curTaskName() : Linux::ThreadInfo
• curTaskPID() : Linux::ThreadInfo
• curTaskStart() : Linux::ThreadInfo
• curTaskTGID() : Linux::ThreadInfo
• curThread : BaseSimpleCPU
• curThreadInfo() : Linux::ThreadInfo
• curTime : MC146818
• curTranType : ArmISA::TLB
• CuSidePort() : LdsState::CuSidePort
• CustomNoMaliGpu() : CustomNoMaliGpu
• cv : DistIface::Sync , SparcISA::PageTableEntry
• cvec : Stats::DistData , Stats::DistStor , Stats::FormulaInfoProxy< Stat > , Stats::HistStor , Stats::Vector2dInfo , Stats::VectorInfoProxy< Stat >
• CvtInst() : HsailISA::CvtInst< DestDataType, SrcDataType >
• cwd : Process
• cwp : SparcISA::ISA
• cx_config : SparcISA::TLB
• cx_tsb_ps0 : SparcISA::TLB
• cx_tsb_ps1 : SparcISA::TLB
• CxxConfigFileBase() : CxxConfigFileBase
• CxxConfigManager() : CxxConfigManager
• CxxConfigParams() : CxxConfigParams
• CxxIniFile() : CxxIniFile
• cycle : Clocked
• cycleCounter : ArmISA::PMU
• Cycles() : Cycles
• cyclesBeforeInsert() : Minor::FUPipeline
• cyclesPerFrame() : DisplayTimings
• cyclesPerLine() : DisplayTimings
• cyclesSinceLastStopped() : Ticked
• cyclesToTicks() : Clocked
• cyl_high : CommandReg
• cyl_low : CommandReg